ViA: A Novel Vision-Transformer Accelerator Based on FPGA — Critical Review Report

Academic fraud report · Geng Detector

Summary

This report presents a highly suspicious assessment of the TCAD 2022 paper 'ViA: A Novel Vision-Transformer Accelerator Based on FPGA' (DOI: 10.1109/TCAD.2022.3197489). The verdict is highly suspicious, driven primarily by a systematic 10× arithmetic error in throughput calculations appearing in both Section IV-B and IV-C. The authors claim an inference throughput of 2.86×10^5 inf/s based on a 100 MHz operating frequency and a ~3.5×10^3 cycle per-stage latency, yet basic division yields only ~2.857×10^4 inf/s. Additional concerns include a misattributed reference where 'RoBERTa' (the well-known NLP model by Liu et al., 2019) is cited via a 2020 paper on a Romanian BERT model, contradictory language describing GPU performance ('improvement' of 0.826×, which is actually a degradation), and the repeated misspelling of 'peak' as 'peek' in abstract and conclusion. The unusually rapid 9-day submission-to-acceptance timeline is explained by the ESWEEK-TCAD special issue route. Confidence is moderate; findings on the 10× arithmetic error and reference misattribution are strong, while intent (deliberate vs. careless) cannot be determined from the report alone.

Verdict

Highly suspicious. The paper contains a reproducible 10× arithmetic discrepancy in core performance figures, a clearly misattributed citation, and contradictory wording in performance comparisons. While the rapid acceptance timeline is consistent with a conference-to-journal special issue route, the accumulation of errors raises serious concerns about rigor in the central quantitative claims.

Key findings

Systematic 10× throughput calculation error (high severity): In Sections IV-B (Norm Self-Attention Module) and IV-C (Norm Multilayer Perceptron Module), the stated inference throughput of 2.86×10^5 inf/s is inconsistent with the stated 100 MHz frequency and ~3.5×10^3 cycle per-stage latency. Basic arithmetic gives 10^8 / (3.5×10^3) ≈ 2.857×10^4 inf/s, exactly one order of magnitude lower than reported. The error appears twice in independent sections.
Misattributed reference (medium severity): Reference [7], cited in the introduction for 'RoBERT' in the NLP context, corresponds to a 2020 paper on a Romanian-language BERT model ('Robert—A romanian bert model'). The well-known RoBERTa model (Liu et al., 2019) is not the cited work.
Contradictory performance language (medium severity): Section VI-C states 'Compared to GPU, the performance improvement is 0.826×.' A value below 1× indicates ViA underperforms the V100 GPU, contradicting the 'improvement' framing. The abstract instead highlights a 5.2× energy-efficiency improvement, which may obscure the lower absolute compute throughput.
Repeated spelling errors (medium severity): 'peek' is used in place of 'peak' in both the abstract and conclusion when describing the 309.6 GOP/s figure.
Rapid acceptance timeline (not a finding): The 9-day submission-to-acceptance interval is explained by the paper being part of the ESWEEK-TCAD special issue, presented at CODES+ISSS 2022. Tools (Vitis 2021.2, Xilinx Alveo U50) are temporally consistent.

Evidence highlights

DOI: 10.1109/TCAD.2022.3197489
Stated operating frequency: 100 MHz (1×10^8 Hz)
Stated per-stage latency: ~3.5×10^3 cycles
Stated throughput (reported): 2.86×10^5 inf/s
Throughput from stated inputs: ≈ 2.857×10^4 inf/s (≈ 10× lower than reported)
Reference [7] title (as cited): 'Robert—A romanian bert model'
Comparison phrasing: 'performance improvement is 0.826×' versus V100 GPU
Peak figure cited: 309.6 GOP/s; the word 'peek' appears in both Abstract and Conclusion
Submission date: 17 July 2022; acceptance date: 26 July 2022 (ESWEEK-TCAD special issue, CODES+ISSS 2022)

Notes

Intent (carelessness versus fabrication) cannot be established from this report alone. An erratum or author response clarifying the throughput derivation and the RoBERTa reference would substantially resolve concerns.
The HLS synthesis reports and on-board test logs were not independently inspected; verification of the 309.6 GOP/s and 2.86×10^5 inf/s figures is recommended.
The 10× discrepancy is the single most consequential issue because it directly affects the headline performance numbers used in the paper's claims versus prior accelerators.