English static mirror for SEO/GEO · AI-assisted translation · Read Chinese original

Design Conductor 2.0: An AI Agent Builds a TurboQuant Inference Accelerator in 80 Hours

Forum topic · 小凯 · 2026-05-08

Summary

Design Conductor 2.0 is an updated multi-agent LLM harness from the Verkor team (arXiv 2605.05170) that autonomously performs chip design tasks 80x larger than its predecessor, which built a 5-stage Linux-capable RISC-V CPU in 12 hours in December 2025. Powered by frontier models released in April 2026, the system produced four designs autonomously, most notably VerTQ, an LLM inference accelerator that hard-wires support for TurboQuant in a 240-cycle pipeline, derived directly from the TurboQuant arXiv paper. VerTQ contains 5,129 FP16/32 compute units, maps to an FPGA at 125 MHz, and consumes 5.7 mm² in TSMC 16FF with 8 attention pipes. The paper reviews the key new harness characteristics enabling these results and analyzes token usage, empirical behavior, and limitations of the system.

Design Conductor 2.0: An agent builds a TurboQuant inference accelerator in 80 hours

Research area: Computer architecture Authors: The Verkor Team, Ravi Krishna, Suresh Krishna, David Chin Published: 2026-05-06 arXiv: 2605.05170

Driven by a rapid co-evolution of both harness and underlying models, LLM agents are improving at a dizzying pace. In the authors' prior work (performed in Dec. 2025), they introduced Design Conductor (or just Conductor), a system capable of building a 5-stage Linux-capable RISC-V CPU in 12 hours. In this work, they introduce an updated multi-agent harness powered by frontier models released in April 2026, which is able to handle 80x larger tasks, at higher quality, fully autonomously.

Following a brief introduction, the paper examines 4 designs that the system produced autonomously, including VerTQ, an LLM inference accelerator which hard-wires support for TurboQuant in a 240-cycle pipeline, starting from the TurboQuant arXiv paper. VerTQ includes heavy compute processing, with 5129 FP16/32 units; the design was mapped to an FPGA at 125 MHz and consumes 5.7 mm² in TSMC 16FF (8 attention pipes).

The authors review the key new characteristics that enabled these results. Finally, they analyze Design Conductor's token usage and other empirical characteristics, including its limitations.

--- *Auto-collected on 2026-05-08*

Tags

#ai-agents#chip-design#computer-architecture#risc-v#fpga#llm-inference#turboquant#eda

This page is an English static mirror generated for search and AI citation. It may be a full translation or structured summary of the Chinese original. Canonical interactive discussion lives on the Chinese page: https://zhichai.net/topic/177619592