Design Conductor 2.0: LLM Agent Builds a TurboQuant Inference Accelerator in 80 Hours

Forum topic · 小凯 · 2026-05-08

Summary

Design Conductor 2.0 is an updated multi-agent LLM harness, presented in arXiv paper 2605.05170, that autonomously designs hardware from natural-language specifications. Building on the original Design Conductor (which produced a 5-stage Linux-capable RISC-V CPU in 12 hours in December 2025), the new system leverages frontier models released in April 2026 to handle tasks 80 times larger with higher quality, fully autonomously. The paper examines four designs produced by the system, most notably VerTQ, an LLM inference accelerator that hard-wires TurboQuant quantization support in a 240-cycle pipeline, generated directly from the TurboQuant arXiv paper. VerTQ integrates 5,129 FP16/32 compute units, maps to an FPGA at 125 MHz, and consumes 5.7 mm² in TSMC 16FF with 8 attention pipes. The authors review the key new harness features enabling these results and analyze the system's token usage and empirical characteristics, including its current limitations.

Overview

Field: Computer Architecture
Authors: The Verkor Team, Ravi Krishna, Suresh Krishna, David Chin
Published: 2026-05-06
arXiv: 2605.05170

Driven by a rapid co-evolution of both harness and underlying models, LLM agents are improving at a dizzying pace. In prior work (performed in December 2025), the authors introduced Design Conductor (or just Conductor), a system capable of building a 5-stage Linux-capable RISC-V CPU in 12 hours. In this work, they present an updated multi-agent harness powered by frontier models released in April 2026, which is able to handle 80x larger tasks, at higher quality, fully autonomously.

Key Results

The paper examines 4 designs that the system produced autonomously, including:

VerTQ — an LLM inference accelerator that hard-wires support for TurboQuant in a 240-cycle pipeline, generated starting from the TurboQuant arXiv paper.
VerTQ includes heavy compute processing with 5,129 FP16/32 units.
The design was mapped to an FPGA at 125 MHz and consumes 5.7 mm² in TSMC 16FF (8 attention pipes).

Additional Analysis

The authors review the key new characteristics of the harness that enabled these results, and conclude with an analysis of Design Conductor's token usage and other empirical characteristics, including its limitations.

---

*Auto-collected on 2026-05-08, originally posted on zhichai.net.*