Sub-Microwatt Inference Chips: Running RNNs on Analog Circuits

Forum topic · 小凯 · 2026-05-18

Summary

Always-on AI applications such as environmental sensors and biomedical implants require extremely low power, but digital chips hit a floor that analog circuits can break through to reach sub-microwatt inference. The historical obstacle: analog signals accumulate noise as they pass through temporal feedback loops, so analog neural networks have been limited to feedforward architectures. A paper by Fyon et al. (arXiv:2605.15216) proposes a way around this using a recurrent neural network called the Bistable Memory Recurrent Unit (BMRU), whose discrete outputs and hysteresis-based internal dynamics suppress analog noise by at least 20x at each unit boundary, breaking the accumulation of noise across time. The authors designed a current-mode analog implementation from first principles, mapping each learnable parameter to a circuit element. Transistor-level simulation on 180nm CMOS shows circuit behavior nearly identical to software predictions, achieving sub-microwatt RNN inference for keyword spotting. Open questions remain about portability to advanced nodes (28nm, 7nm) and the expressiveness of discrete outputs compared to LSTMs or Transformers.

Always-On AI Needs a Lower Power Floor

"Always-on AI" applications—environmental sensors, biomedical implants—demand extremely low power consumption. Digital chips hit a floor below which they cannot go, while analog circuits can achieve sub-microwatt-level inference. But there has long been an obstacle: analog signals accumulate noise as they pass through temporal feedback loops, so analog implementations of neural networks could only do feedforward computation, not recurrence.

The Breakthrough: Bistable Memory Recurrent Units

Fyon et al. (arXiv:2605.15216) found a way through: a class of RNNs called BMRU (Bistable Memory Recurrent Unit), whose output is discrete and whose internal dynamics exhibit hysteresis. The discrete output suppresses analog noise by at least 20x at each unit boundary, interrupting the accumulation of noise in temporal feedback.

Circuit Design and Results

The authors designed a current-mode analog implementation from first principles, with each learnable parameter corresponding to one circuit element. Transistor-level simulation on a 180nm CMOS process showed that software predictions and circuit behavior were nearly identical.

Keyword spotting was demonstrated with the RNN core running at sub-microwatt inference power.

Open Questions

Process node scaling: 180nm is an old node. How would analog noise characteristics and leakage current change on more advanced nodes (28nm or 7nm)? The paper claims "scalability" but offers no cross-node validation.
Task coverage: What classes of sequence tasks can BMRUs handle in modern deep learning?
Expressiveness: Can discrete-output BMRUs match the expressiveness of LSTMs or Transformers?

References

1. Fyon, A., et al. (2026). *Hardware-Software Co-Design of Scalable, Energy-Efficient Analog Recurrent Computations*. arXiv:2605.15216 [cs.AR]. 2. Jakesch, A., et al. (2024). *Bistable Memory Recurrent Units*. NeurIPS 2024. 3. Mead, C. (1990). *Neuromorphic Electronic Systems*. Proceedings of the IEEE, 78(10), 1629-1636. 4. Verhoef, B., et al. (2023). *Sub-microwatt Keyword Spotting with Analog Circuits*.