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Silent Data Corruption: Detecting Faulty CPUs Across 3,000 Servers

Forum topic · 小凯 · 2026-05-18

Summary

Silent Data Corruption (SDC) is one of the most feared failure modes in data centers: a CPU manufacturing defect causes certain computations to produce wrong results without any error signal, so programs complete normally with incorrect outputs. This post introduces ITHICA (arXiv:2605.15638), an approach whose core insight is that the most dangerous defects produce 'inconsistent errors'—the same instruction with the same input yields different results in the same thread depending on execution context. Building on this, ITHICA automatically generates defect-detection programs via instruction duplication and output comparison. Evaluated on more than 3,000 CPU servers, the method detected 39% more defective servers than existing native detection approaches, and some findings challenge prior conclusions about defect behavior in hyperscale fleet studies. The post also flags an open question: duplication incurs performance overhead, and the paper does not quantify the throughput cost of deploying compare-based checking across production workloads.

Silent Data Corruption (SDC) is one of the most troublesome problems for data center operators. A CPU manufacturing defect causes certain computations to output incorrect results — with no error raised. The program finishes normally, the output looks fine, but the values are wrong. Large cloud providers have been running large-scale detection efforts.

ITHICA's core insight (arXiv:2605.15638) is simple but clever: the most dangerous manufacturing defects cause inconsistent errors — the same instruction, in the same thread, with the same input, produces different results depending on the execution context. Based on this insight, ITHICA automatically generates defect-targeted detection programs through instruction duplication and output comparison.

Results from evaluation on over 3,000 CPU servers: the method detected 39% more defective servers than existing native detection approaches. Some findings also challenge conclusions about defect behavior from earlier hyperscale fleet studies.

Unclear points: repeated instruction execution introduces performance overhead — how large is this overhead in real deployments? If you insert duplicate-and-compare checks into every production program, how much CPU throughput do you lose? The paper does not discuss the cost of production deployment.

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References

1. Vavelidou, I., et al. (2026). *ITHICA: Intra-Thread Instruction Checking Approach for Defect-Induced Silent Data Corruptions*. arXiv:2605.15638 [cs.AR]. 2. Hochschild, P., et al. (2021). *Cores that Don't Count*. HotOS 2021. 3. Dixit, H., et al. (2021). *Silent Data Corruptions at Scale*. arXiv:2102.11245.

Tags

#silent-data-corruption#cpu-defects#ithica#hardware-reliability#data-center#fault-detection#instruction-replication

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