Imagine standing in a giant library where every book tells you the location of the next one. You open one, find the next target, walk there, open it, and walk again. That is a GPU's daily routine during ray tracing: each ray traverses a huge BVH tree, and most of the time is spent not computing but waiting for memory to deliver the next level of tree nodes.
The Problem Is the Tree, Not the Rays
The Bounding Volume Hierarchy encodes a 3D scene as a large binary tree. Every ray cast by the GPU starts a search from the root, testing intersection with bounding boxes level by level until it reaches the triangles at the leaves. A single traversal reads dozens of nodes, each scattered across different corners of VRAM. Despite thousands of cores, most sit idle during BVH traversal—waiting for data to arrive, for cache hits, for the next wave of memory requests.
TTP: Free Information from the Traversal Stack
The TTP prefetcher proposed by Tozlu, Naithani, and Zhou starts from a simple observation: the GPU's ray tracing hardware units already maintain a stack during BVH traversal, holding the addresses of nodes not yet visited along the current path. Since those addresses are already there, why not fetch them into cache ahead of time?
Rather than a complex prediction algorithm, TTP picks low-hanging fruit from an existing data structure:
- During depth-first traversal, the hardware repeatedly pops nodes from the stack; each pop means backtracking one level upward.
- TTP detects these consecutive pops—meaning the ray just finished a subtree and is heading back up—and prefetches the nodes of the next level to be visited into L1 cache.
- No dedicated predictor, no history tables: it relies purely on address information already present in the hardware traversal stack.
- Average performance improvement of 1.48x, up to 1.89x.
- 98.92% L1 prefetch accuracy—nearly 99% of prefetched data is actually consumed by later requests, wasting almost no bandwidth.
- L1 misses reduced by 31.54%, consistent with the speedup figures.
- The paper validates at the simulator level only; it has not been run on real silicon. The gap between simulator and actual hardware may be nontrivial—especially the bandwidth and latency parameters between L1 and L2, whose critical thresholds differ on real chips.
- TTP depends on the specific pattern of consecutive pops in DFS traversal. Whether it remains effective under future non-DFS traversal algorithms is not discussed in the paper.
Results
Evaluated on the Vulkan-sim 2.0 cycle-accurate simulator:
Caveats
References
1. Tozlu, Y. S., Naithani, A., & Zhou, H. (2026). *TTP: A Hardware-Efficient Design for Precise Prefetching in Ray Tracing*. arXiv:2605.16253 [cs.AR]. 2. Wald, I., et al. (2019). *Embree: A Kernel Framework for Efficient CPU Ray Tracing*. ACM Transactions on Graphics. 3. Mehta, D. U., et al. (2023). *Vulkan-Sim: A GPU Architecture Simulator for Vulkan*. IEEE International Symposium on Performance Analysis of Systems and Software.