Compute-in-SRAM: XNOR and Adder Logic Built into a 10T SRAM Cell

Forum topic · 小凯 · 2026-05-18

Summary

A Chinese tech forum post discusses a compute-in-memory SRAM design by Dhakad and Vishvakarma aimed at AI accelerator MAC (multiply-accumulate) workloads. Conventional AI accelerators move data from SRAM arrays to separate compute units and write results back, causing congested interconnect, area overhead, and power costs as arrays scale. The proposed approach embeds computation directly inside SRAM cells: a 10T SRAM cell with built-in XNOR logic performs the core operation of binary neural networks, where weights and activations are constrained to +1 and -1, allowing multiplication to be replaced by XNOR. Weights stay in place while activations arrive via bit lines, producing products directly on the bit lines. The design also replaces the traditional 28-transistor full adder with a 14-transistor version, halving adder-tree area, and builds N-bit ripple-carry adders from these cells. Reported results include 50% reduction in routing complexity and 2.67x area-efficiency improvement over prior state of the art. The author raises open questions: the larger footprint of 10T versus standard 6T cells may not be fully accounted for, and no end-to-end accuracy analysis is provided despite XNOR accuracy depending heavily on task and quantization strategy.

AI accelerators normally handle multiply-accumulate (MAC) operations by reading data out of SRAM into a compute unit, multiplying and accumulating, then writing the result back. But the data path between reads and writes is getting increasingly congested — especially with large SRAM arrays, where bringing every MAC result out from deep inside the memory array requires extensive metal routing. Those wires consume chip area, burn power, and limit clock frequency.

The design by Dhakad and Vishvakarma takes a different approach: since routing inside the SRAM array is already the bottleneck, don't extract MAC results at all — let the data compute inside the SRAM storage cells themselves.

XNOR inside the cell

They chose a 10T SRAM cell to perform the XNOR operation. A standard 6T SRAM cell can only store a bit; the 10T variant embeds XNOR logic inside the storage cell — the core operation of binary neural networks (BNNs). In BNNs, weights and activations take only +1 and -1 values, and replacing multiplication with XNOR can reduce area and power by one to two orders of magnitude. The problem has always been that data movement between storage and compute consumes most of the cost. Putting XNOR directly into the SRAM cell means: weights stay where they are, activations arrive over the bit lines, and the product is generated right on the bit lines.

A leaner adder tree

The adder tree was also streamlined. The traditional 28-transistor full adder is replaced by a 14-transistor version — area cut in half. An N-bit ripple-carry adder built from this reduced adder correspondingly halves the transistor count along the accumulation path.

Overall effect

Routing complexity reduced by 50%
Overall area efficiency improved by 2.67x versus existing state-of-the-art solutions

Open questions

Unclear points: a 10T SRAM cell is larger than a standard 6T cell — is this area penalty fully accounted for in the overall design? The paper reports 50% routing complexity reduction but does not mention the area inflation of the SRAM cells themselves. Accuracy analysis is also missing — XNOR accuracy in binary networks depends heavily on the specific task and quantization strategy, and the paper provides no end-to-end accuracy data.

References

1. Dhakad, N. S., & Vishvakarma, S. K. (2026). *SRAM Based Digital Custom Compute Engine for Improved Area Efficiency of AI Hardware*. arXiv:2605.16161 [cs.AR]. 2. Courbariaux, M., et al. (2016). *Binarized Neural Networks: Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1*. NeurIPS. 3. Agrawal, A., et al. (2018). *XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks*. IEEE Journal of Solid-State Circuits.