In-SRAM Computing: XNOR and Adder Logic in a 10T SRAM Cell for AI Accelerators

Forum topic · 小凯 · 2026-05-18

Summary

A forum post discusses a design by Dhakad and Vishvakarma that moves multiply-accumulate (MAC) computation into SRAM storage cells to overcome the data-routing bottleneck in AI accelerators. Traditional architectures shuttle data between SRAM arrays and compute units, with metal wiring dominating area, power, and clock constraints. The proposed design uses a 10T SRAM cell with embedded XNOR logic—the core operation of binary neural networks—so weights stay in place while activations arrive via bit lines and products form directly on them. The adder tree is also streamlined: a 14-transistor full adder replaces the conventional 28-transistor version, halving the transistor count in N-bit ripple-carry accumulation paths. Reported results include 50% lower routing complexity and a 2.67x area-efficiency improvement over prior state-of-the-art designs. The post also raises criticisms: the 10T cell's area overhead versus standard 6T cells is not accounted for, and accuracy analysis is missing, since XNOR-based binary network performance depends heavily on the task and quantization strategy. References include arXiv:2605.16161, Courbariaux et al.'s Binarized Neural Networks (NeurIPS 2016), and Agrawal et al.'s XNOR-SRAM (IEEE JSSC 2018).

The problem: the data path between SRAM and compute units

The standard approach for multiply-accumulate (MAC) operations in AI accelerators: read data from SRAM into compute units, multiply and accumulate, then write results back. But the data path between reads and writes is increasingly congested—especially with large SRAM arrays, where bringing every MAC result out from deep inside the memory array requires extensive metal routing. These wires consume chip area, burn power, and limit clock frequency.

The approach: compute inside the storage cell

The design by Dhakad and Vishvakarma takes a different route: since routing inside the SRAM array is already the bottleneck, don't bring MAC results out—let the data compute inside the SRAM storage cells themselves.

Key elements:

10T SRAM cell with embedded XNOR logic. A standard 6T SRAM cell can only store bits; the 10T version embeds XNOR logic inside the storage cell—XNOR being the core operation of binary neural networks (BNNs). In BNNs, weights and activations are only +1 and -1, and replacing multiplication with XNOR can reduce area and power by one to two orders of magnitude. The remaining cost is data movement between memory and compute. Embedding XNOR directly into the SRAM cell means weights stay in place, activations arrive over the bit lines, and products are produced on the bit lines themselves.
Streamlined adder tree. The conventional 28-transistor full adder is replaced by a 14-transistor version—halving the area directly. An N-bit ripple-carry adder built from this reduced adder similarly halves the transistor count in the accumulation path.

Reported results

Routing complexity reduced by 50%
Overall area efficiency improved by 2.67x compared to the best existing designs

Open questions raised in the post

A 10T SRAM cell is larger than a standard 6T cell—was this area overhead fully accounted for in the overall design? The paper claims 50% lower routing complexity but doesn't discuss the SRAM cell's own area expansion.
Accuracy analysis is missing. XNOR operation accuracy in binary networks depends heavily on the specific task and quantization strategy, and the paper provides no end-to-end accuracy numbers.

References

1. Dhakad, N. S., & Vishvakarma, S. K. (2026). *SRAM Based Digital Custom Compute Engine for Improved Area Efficiency of AI Hardware*. arXiv:2605.16161 [cs.AR]. 2. Courbariaux, M., et al. (2016). *Binarized Neural Networks: Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1*. NeurIPS. 3. Agrawal, A., et al. (2018). *XNOR-SRAM: In-Memory Computing SRAM Macro for Binary/Ternary Deep Neural Networks*. IEEE Journal of Solid-State Circuits.