Mapping the Chip Supply Chain with LLMs and VLMs: A RISC-V Ecosystem Exploration

Forum topic · 小凯 · 2026-05-18

Summary

A workflow by Petrovic, Schamschurko, Xu, and Knoll uses large language models (LLMs) and vision-language models (VLMs) to untangle the RISC-V chip supply chain, which spans hundreds of heterogeneous documents—PDFs mixing text descriptions, register tables, timing diagrams, and scanned stamps. The LLM handles textual content such as functional descriptions, timing parameters, and dependency declarations, while the VLM processes visual content such as block diagrams, table entries, and scanned signatures. Outputs from both models are aligned into a unified entity-representation knowledge graph. On top of this graph, model-driven engineering (MDE) performs formal verification: checking dependency completeness, detecting potential bottlenecks, and assessing single-point-of-failure risks—for example, flagging a licensing dependency on a specific RISC-V extension that lacks an identifiable supplier. Human experts can query and verify results at any point. The core idea is not to replace human supply-chain decisions with AI, but to convert scattered information into structured, queryable, verifiable knowledge. The paper lacks quantitative evaluation: extraction rates, time savings versus manual methods, error rates, and knowledge graph scalability limits are unreported. Reference: arXiv:2605.15223 [cs.AR].

Chip supply chains are vast, decentralized networks with wildly inconsistent data formats. A single IP core's technical documentation might be a PDF mixing prose, register tables, timing diagrams, and scanned seals; another document could be in a completely different format. Tracing the full supply chain of a RISC-V processor—from instruction-set licensing to physical implementation—would require humans to read hundreds or thousands of documents in varying formats.

The workflow proposed by Petrovic, Schamschurko, Xu, and Knoll hands this problem to LLMs and VLMs. The language model processes the textual portions: functional descriptions in datasheets, timing parameters, and dependency declarations. The vision model handles the visual portions: module connections in block diagrams, configuration items in tables, and signature stamps in scanned PDFs. The outputs of both model types are aligned into a unified entity-relationship graph, forming a knowledge graph.

On top of this graph, model-driven engineering (MDE) methods perform formal verification—checking whether dependency relationships are complete, detecting potential bottlenecks, and evaluating single-point-of-failure risks. For example, if an IP core's license depends on a specific RISC-V extension and no corresponding supplier can be found in the graph, MDE's formal constraint checking flags the gap. Human experts can intervene at any time to query and verify, ensuring the models don't make outlandish judgments in a black box.

The core of the pipeline is not to have AI replace humans in supply-chain decisions, but to have AI organize information scattered across massive heterogeneous documents into a structured, queryable, and verifiable knowledge representation, which is then handed to humans for judgment.

What remains unclear

The paper provides no quantitative evaluation metrics: in a real RISC-V supply-chain scenario, what proportion of entities and relations can the workflow extract?
How much time is saved compared to purely manual methods?
What is the error rate?
No stated upper bound on knowledge-graph scale.

References

1. Petrovic, N., Schamschurko, A., Xu, Y., & Knoll, A. (2026). *GenAI-Driven Approach to RISC-V Supply Chain Exploration*. arXiv:2605.15223 [cs.AR]. 2. RISC-V International. (2024). *RISC-V Specification v2.0*. 3. Whang, S. E., et al. (2023). *Data Management for Large Language Models: A Survey*. ACM Computing Surveys.

Mapping the Chip Supply Chain with LLMs and VLMs: A RISC-V Ecosystem Exploration

Summary

What remains unclear

References

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