Mapping the Chip Supply Chain with LLMs and VLMs: A RISC-V Ecosystem Exploration

Forum topic · 小凯 · 2026-05-18

Summary

A Chinese forum post discusses a GenAI-driven workflow for exploring the RISC-V chip supply chain, based on a paper by Petrovic, Schamschurko, Xu, and Knoll (arXiv:2605.15223). Chip supply chains span vast numbers of heterogeneous documents—PDFs mixing text, register tables, timing diagrams, and scanned stamps. The proposed pipeline assigns large language models (LLMs) to textual content such as datasheet descriptions, timing parameters, and dependency declarations, while vision-language models (VLMs) handle graphical content like block diagrams, configuration tables, and scanned signatures. Outputs from both model types are aligned into a unified entity-relationship knowledge graph. On top of this graph, model-driven engineering (MDE) performs formal verification: checking dependency completeness, detecting bottlenecks, and assessing single-point-of-failure risks—for example, flagging an IP core's licensing dependency on a RISC-V extension with no identified supplier. The author emphasizes that the goal is not to replace human decision-making but to structure scattered information into queryable, verifiable knowledge for expert review. The post also notes limitations: the paper lacks quantitative evaluation metrics such as entity/relation extraction rates, time savings versus manual analysis, error rates, and knowledge graph scale limits.

Background

The chip supply chain is a vast, distributed network with wildly heterogeneous data formats. A technical document for an IP core might be a PDF mixing prose, register tables, timing diagrams, and scanned seals; another document could use an entirely different format. Tracing the full supply chain of a RISC-V processor—from instruction set licensing to physical implementation—would require humans to read hundreds or thousands of differently formatted documents.

The LLM + VLM Workflow

The workflow by Petrovic, Schamschurko, Xu, and Knoll hands this problem to LLMs and VLMs:

LLMs handle the textual portions: functional descriptions in datasheets, timing parameters, and dependency declarations.
VLMs handle the visual portions: module connections in block diagrams, configuration entries in tables, and signature stamps in scanned PDFs.

Outputs from both model types are aligned into a unified entity-relationship graph, forming a knowledge graph.

Formal Verification via Model-Driven Engineering

On top of this graph, model-driven engineering (MDE) methods perform formal verification—checking whether dependencies are complete, detecting potential bottlenecks, and evaluating single-point-of-failure risks. For example, if an IP core's licensing depends on a specific RISC-V extension and no corresponding supplier can be found in the graph, MDE's formal constraint checking flags the gap. Human experts can query and verify at any point, ensuring the models don't make wild judgments inside a black box.

The Core Idea

The point of the pipeline is not to have AI replace humans in supply chain decisions, but to have AI organize information scattered across massive heterogeneous documents into a structured, queryable, verifiable knowledge representation—then hand judgment back to humans.

Open Questions

The paper does not provide quantitative evaluation metrics:

What proportion of entities and relations can this workflow extract in a real RISC-V supply chain scenario?
How much time does it save compared to purely manual methods?
What is the error rate?
What is the scalability ceiling of the knowledge graph?

References

1. Petrovic, N., Schamschurko, A., Xu, Y., & Knoll, A. (2026). *GenAI-Driven Approach to RISC-V Supply Chain Exploration*. arXiv:2605.15223 [cs.AR]. 2. RISC-V International. (2024). *RISC-V Specification v2.0*. 3. Whang, S. E., et al. (2023). *Data Management for Large Language Models: A Survey*. ACM Computing Surveys.