Chip design has an open secret: AI models that generate RTL code perform well in academic benchmarks but are almost never used in industry. The reason is not that the models write bad code — it is a fundamental mismatch between real industrial workflows and academic evaluation setups.
Academic evaluation assumes a perfect golden testbench exists before the model writes code. In reality, testbenches are often developed alongside the design; there is no golden reference until the code is done. Academic evaluation assumes the model can call closed-source APIs. In reality, chip vendors' servers are physically air-gapped — no outbound data allowed. Academic evaluation assumes models cannot be fine-tuned on proprietary codebases. In reality, every chip company holds decades of proprietary RTL, but that data can neither be uploaded to the cloud nor used for training.
ChipMATE, proposed by Yu, Lin, and their team, changes this paradigm at its root. The core design uses two agents: one writes Verilog (the hardware description language), and one writes a Python reference model (a software behavioral description). After the Verilog agent produces an RTL segment, the Python agent independently writes a corresponding reference model. The two outputs are compared against each other — not against an external golden reference; each acts as the other's validation standard. This mirrors a common industrial practice: two engineers independently design the same module, then cross-verify.
Even more critical is the training pipeline, which has two stages. Stage one trains each agent independently, pushing each one's code generation ability to saturation. Stage two is joint training, teaching the pair to collaborate — one agent learns the other's needs, writing code that is easy for the partner to verify, and producing reference models that are easy for the partner to understand. Both stages are driven by reinforcement learning.
At inference time there is also a backtracking mechanism: if one agent's output causes the other agent's validation to fail, the workflow does not continue; instead, it backtracks to the previous decision point and regenerates. This prevents errors from propagating across turns.
The results are striking. ChipMATE achieves 75.0% pass@1 on VerilogEval V2 with a 4B base model, and 80.1% with a 9B model. Every record previously held by self-trained models was broken. More notably, the 9B version of ChipMATE even surpasses DeepSeek V4 — a general-purpose giant with 1600B parameters. Two specialized agents totaling under 20B parameters beat a 1600B general-purpose colossus.
Unclear points: the paper's training data consists of 64.4K samples generated by the framework itself — how is their quality guaranteed? If the reference-model agent has itself learned wrong patterns, cross-validation could become cross-confirmation. Also, the training stability of multi-agent reinforcement learning has been contested in similar systems — could collapse modes emerge, where the two agents settle into a low-quality mutual默契-style equilibrium?
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References
1. Yu, Z., Lin, Y., Zhou, C., et al. (2026). *ChipMATE: Multi-Agent Training via Reinforcement Learning for Enhanced RTL Generation*. arXiv:2605.12857 [cs.MA]. 2. Thakur, S., et al. (2024). *VerilogEval: Evaluating Large Language Models for Verilog Code Generation*. DAC. 3. Wu, M., et al. (2025). *RTLCoder: Fully Open-Source and Efficient LLM for RTL Code Generation*. DATE.