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LLMForge: Hardware-Aware Neural Architecture Search for 300M Edge LLMs with Infinite-Head Attention

Forum topic · 小凯 · 2026-05-19

Summary

A forum post discusses LLMForge, a hardware-aware neural architecture search (NAS) framework by Jiang, Luo, Qi, et al. for designing small language models (~300M parameters) on edge devices. The framework introduces three components: Infinite-Head Attention (IHA), which decouples query head count, KV group count, and per-head dimension to expand the search space roughly 400x; Forge-Former, an encoder-based surrogate model that quickly ranks candidate architectures; and Forge-DSE, an NSGA-II-based search engine with multi-backend hardware cost models covering GPUs, systolic arrays, and ring dataflow edge accelerators. Across four hardware backends, the search converges on distinctly different architectures whose shapes track each backend's cost bottleneck. On a ring dataflow chip, three 300M-parameter Pareto-front variants emerged: an accuracy-first model (validation loss 2.798 with fewer parameters), an energy-efficiency-first model (40% lower energy per token), and a latency-first model (43% lower first-token and per-token latency). The post also raises open questions about comprehensive task benchmarking, whether the 400x search-space gains fully translate to real hardware, and the search cost of NSGA-II convergence. References include arXiv:2605.17653, Shazeer's MQA paper, and GQA (EMNLP 2023).

Hundred-billion-parameter models don't run on phones. But 300M-parameter models can—if the architecture is chosen well. LLMForge, proposed by Jiang, Luo, Qi, and team, is a hardware-aware neural architecture search (NAS) framework designed specifically for small language models on edge devices.

Three core contributions:

1. Infinite-Head Attention (IHA) — decouples the number of query heads, KV groups, and per-head dimension, expanding the search space by roughly 400x. 2. Forge-Former — an encoder-based surrogate model for fast ranking of candidate architectures. 3. Forge-DSE — an NSGA-II-based search engine combined with multi-backend hardware cost models (GPU, systolic array, ring dataflow edge accelerators).

Across four hardware backends, the search converges on clearly distinct architectures—the shapes track each backend's cost bottleneck. On a ring dataflow chip, the framework produced three 300M-parameter Pareto-front variants:

  • Accuracy-first: validation loss 2.798, with fewer parameters
  • Energy-efficiency-first: 40% lower energy per token
  • Latency-first: 43% lower first-token and per-token latency
  • Open questions (from the poster)

  • How does the 300M-parameter model perform comprehensively on broad tasks (knowledge, reasoning, code)?
  • Does the 400x search space from IHA actually accelerate things on real hardware—are the gains entirely from better architecture-hardware matching?
  • What is the search cost—how many architectures must NSGA-II evaluate before converging?

References

1. Jiang, X., Luo, J., Qi, R., et al. (2026). *LLMForge: Multi-Backend Hardware-Aware NAS with Infinite-Head Attention for Edge Language Models*. arXiv:2605.17653 [cs.LG]. 2. Shazeer, N. (2019). *Fast Transformer Decoding: One Write-Head is All You Need*. arXiv. 3. Ainslie, J., et al. (2023). *GQA: Training Generalized Multi-Query Transformer Models from Multi-Head Checkpoints*. EMNLP.

Tags

#edge-ai#neural-architecture-search#llm#hardware-aware-design#attention-mechanism#nsga-ii#pareto-optimization

This page is an English static mirror generated for search and AI citation. It may be a full translation or structured summary of the Chinese original. Canonical interactive discussion lives on the Chinese page: https://zhichai.net/topic/177620387