English static mirror for SEO/GEO · AI-assisted translation · Read Chinese original

LLMForge: Hardware-Aware NAS with Infinite-Head Attention for 300M Edge LLMs

Forum topic · 小凯 · 2026-05-19

Summary

LLMForge is a hardware-aware neural architecture search framework for small language models (~300M parameters) on edge devices, proposed by Jiang, Luo, Qi and colleagues. It introduces three components: Infinite-Head Attention (IHA), which decouples query head count, KV group count, and per-head dimension to expand the search space roughly 400x; Forge-Former, an encoder-based surrogate model for fast candidate ranking; and Forge-DSE, an NSGA-II-based search engine coupled with multi-backend hardware cost models covering GPUs, systolic arrays, and ring dataflow edge accelerators. Across four hardware backends, the search converges to clearly different architectures whose shapes track each backend's cost bottleneck. On a ring dataflow chip, three 300M-parameter Pareto-front variants emerge: an accuracy-first model (validation loss 2.798 with fewer parameters), an energy-first model (40% lower energy per token), and a latency-first model (43% lower first-token and per-token latency). Open questions include general-purpose task performance of 300M models, whether gains fully stem from better architecture-hardware matching, and the number of architectures NSGA-II must evaluate before converging.

Hundred-billion-parameter models don't run on phones. But 300-million-parameter models can — if the architecture is chosen correctly. LLMForge, proposed by Jiang, Luo, Qi and team, is a hardware-aware neural architecture search (NAS) framework designed specifically for small language models on edge devices.

Three core contributions:

1. Infinite-Head Attention (IHA) — decouples the number of query heads, KV groups, and per-head dimension, expanding the search space by roughly 400x. 2. Forge-Former — an encoder-based surrogate model that rapidly ranks candidate architectures. 3. Forge-DSE — an NSGA-II-based search engine combined with multi-backend hardware cost models (GPU, systolic array, ring dataflow edge accelerator).

Across four hardware backends, the search converges to clearly different architectures — their shapes track each backend's cost bottleneck.

On the ring dataflow chip, the search produced three 300M-parameter Pareto-front variants:

  • Accuracy-first: validation loss 2.798 with fewer parameters
  • Energy-efficiency-first: 40% lower energy per token
  • Latency-first: 43% lower first-token and per-token latency
  • Open Questions

  • How do 300M-parameter models perform comprehensively on broad tasks (knowledge, reasoning, code)?
  • For the 400x search-space expansion from IHA, does the speedup on real hardware come entirely from better architecture-hardware matching?
  • Search cost: how many architectures must NSGA-II evaluate before converging?

References

1. Jiang, X., Luo, J., Qi, R., et al. (2026). *LLMForge: Multi-Backend Hardware-Aware NAS with Infinite-Head Attention for Edge Language Models*. arXiv:2605.17653 [cs.LG]. 2. Shazeer, N. (2019). *Fast Transformer Decoding: One Write-Head is All You Need*. arXiv. 3. Ainslie, J., et al. (2023). *GQA: Training Generalized Multi-Query Transformer Models from Multi-Head Checkpoints*. EMNLP.

Tags

#edge-ai#neural-architecture-search#small-language-models#llmforge#infinite-head-attention#hardware-aware-nas#nsga-ii#energy-efficiency

This page is an English static mirror generated for search and AI citation. It may be a full translation or structured summary of the Chinese original. Canonical interactive discussion lives on the Chinese page: https://zhichai.net/topic/177620387