Key points
Why MLCC may be the "next DRAM"
- MLCC is a highly standardized electronic commodity with violent pendulum-like price swings: expansion of high-end MLCC takes 1.5–2 years (material formulation, precision stacking equipment), so demand surges create supply gaps; downcycles trigger multi-quarter inventory digestion.
- Market concentration mirrors DRAM: Murata, Samsung Electro-Mechanics (SEMCO), and Taiyo Yuden together hold ~65–70% global share; Japanese/Korean vendors exceed 90% in automotive-grade and AI server MLCC, giving them pricing power via utilization control.
- AI creates structural capacity crowding-out, analogous to HBM absorbing DDR5 wafer capacity: high-layer-count, ultra-small high-capacitance MLCCs consume multiples of the production hours of generic parts, compressing commodity output and driving a volume-price supercycle.
- Comparison table highlights: AI servers raise MLCC value per unit 8–10x (vs. 5–10x for memory); capital barriers are high (Japanese equipment chokepoints) but technology lifecycles exceed 10 years, unlike DRAM's 1–2 year process cycles.
- Murata: Vertical integration from barium-titanate powder formulation to coating machines and kilns; stacks 1000+ layers on sub-1µm dielectrics; ~70% of NVIDIA AI server high-end MLCC demand; dominant in automotive safety parts (ABS/ADAS). Weakness: conservative expansion and high prices leave mid/low-end openings.
- SEMCO: Backed by Samsung group capital, pursues aggressive counter-cyclical investment (Tianjin, Philippines lines); AI server high-end MLCC share has climbed to ~30–40%. Weakness: small gap in nanoscale powder formulations and extreme-environment automotive qualification.
- Taiyo Yuden: Differentiation over scale — high-capacitance and RF capacitors, strong in base stations, networking, and EV powertrain inverters. Weakness: smaller capacity, weaker resilience in price wars.
- With GPU voltages falling below 1.0 V (0.75–0.8 V) and dI/dt rising exponentially, Delta-I noise follows ΔV = L_ESL · dI/dt. At 0.8 V, just 80 mV of voltage droop (10%) can crash logic on a server worth tens of thousands of dollars.
- Low-inductance structures:
- Reverse geometry (LWDC, e.g., 0306): wide-side terminals shorten current loops, cutting ESL 50–80%.
- 3-terminal feed-through: internal ground electrode splits high-frequency current; impedance at >100 MHz is an order of magnitude lower.
- Multi-terminal arrays (IDC/LICA): interdigitated BGA/PGA pads mounted die-side on the GPU package substrate.
- For >1200 W transients on Blackwell Ultra-class chips, silicon capacitors built with MOS/semiconductor 3D deep-trench processes offer: sub-50 µm thickness for embedding in package substrates or IPD/interposer integration; picohenry-level ESL (an order of magnitude below LCC); near-zero capacitance drift from −55 °C to +200/+250 °C.
- Murata acquired pioneer IPDiA in 2016 (now Murata Integrated Passive Solutions) and its silicon capacitors appear in Blackwell-era reference PDN designs as the high-frequency decoupling heart.
- MLCC/LCC shows genuine "memory-ization": AI-driven capacity crowding plus Japanese-Korean oligopoly confer DRAM-like price elasticity and strategic chokepoint status.
- Murata remains the undisputed MLCC king (materials self-sufficiency, 1000-layer sintering, silicon capacitor monopoly); SEMCO is the counter-cyclical predator poised to strike if Murata slips on capacity or pricing.
- For Chinese passive-component makers, the path forward requires mastering barium titanate powders, ultra-thin coating equipment, and low-ESL LCC structural processes.
The three contenders (2026 estimated shares: Murata ~35%, SEMCO ~23%, Taiyo Yuden ~11%)
Physics of LCC/LICC in AI power delivery
Silicon capacitors: the next dimension
Conclusion
References cited in the original post
1. Smith, L. D., & Novoso, T. (2018). *Power Distribution Network (PDN) Design for Nanosecond High-Speed Transient Response in Multi-Gigahertz VLSI Systems*. IEEE Transactions on Advanced Packaging, Vol. 41, No. 3, pp. 245-258. 2. Galvagni, J., & Prymak, J. (2020). *Low Inductance Capacitor Array (LICA) and Interdigitated Capacitor (IDC) Design Guidelines for Advanced Microprocessors*. KYOCERA AVX Technical Whitepaper. 3. Ledu, P., & Dubois, J. (2023). *3D Silicon Trench Capacitors for Die-Side and Substrate-Embedded Decoupling in High Performance Computing (HPC) Accelerators*. IMAPS, pp. 112-119.