In a superconducting quantum computer, every physical qubit carries its own set of control lines, readout resonators, and filters. A single logical qubit protected by the surface code may span dozens of physical qubits, so dozens of coaxial lines must run from room temperature down to the coldest stage of a dilution refrigerator, packed into a space smaller than a microwave oven cavity.
A team from Stanford, the University of Chicago, SLAC, and collaborating institutions reports in *Nature Physics* a way around this congestion: retire some qubits from "processor" duty and park them in a multimode aluminum cavity as memory, with a single transmon retrieving them on demand. In the device, one transmon serves seven addressable storage cells.
Why superconducting machines have no memory
In classical computers, processor and memory are separate: CPUs are expensive, fast, and few; memory is cheap, dense, and addressed. Today's superconducting quantum machines use the same physical qubit for both storing information and computing.
David I. Schuster (senior author) framed the problem for Phys.org with the word "refrigerator": in a quantum computer every qubit is a processor qubit, each needing its own microwave electronics and a bundle of lines reaching into an already crowded fridge. If every additional qubit requires more control hardware, scaling shifts from a physics problem to an engineering problem.
The catch is one level deeper: directly connecting a transmon to a multimode cavity causes trouble. As Schuster put it, the transmon induces interactions between the two objects it connects — which is exactly why it is good at computing, and exactly why it disturbs the fragile states you meant to store.
A four-level cascade: processor, buffer, coupler, storage cavity
The device has four parts: a transmon as processor, a multimode aluminum cavity holding seven modes as storage cells, a buffer cavity in between, and a tunable coupler that shuttles quantum states between the buffer and a targeted storage cell.
Schuster likens the buffer cavity to a cache, or a workbench. Selecting a storage cell is like tuning a radio: apply a control tone at the matching frequency to open the swap and bring the selected cell's state into the buffer; the transmon operates on the buffer; the process reverses to write back. Each swap takes roughly half a microsecond, and the other six cells stay put.
Co-first author Eesh Gupta pointed to the crux: fast processing introduces parasitic interactions that would pollute any memory coupled to it; in the cascade, the buffer shields them apart, letting processor and memory each perform at their best.
The processor never talks directly to the storage layer — the intermediate buffer is the fulcrum of the whole design.
Half a microsecond and 1.2 percent
The team's test repeatedly accessed the seven cells thousands of times while applying randomizing operations, tracking how errors accumulate.
A single access introduces about 1.2% error per mode on average — roughly 98.8% fidelity per visit. If errors are independent, accessing the same cell ten times drops cumulative success to about 0.886, i.e., roughly 11% accumulated error over ten accesses. A second account of the paper describes the device as an eight-qubit cascaded random-access quantum memory with average infidelity below 1.5% per mode — consistent in scale with the first figure.
That arithmetic — 11% over ten accesses — is the honest boundary of the current prototype. Until access error rates fall, programs must keep memory round-trips to a minimum.
Error attribution shows residual interactions between modes inside the multimode cavity are the dominant error source. The team itself notes this in the paper as a lead for the next design iteration.
| Metric | Value | Notes | |---|---|---| | Addressable storage cells | 7 modes | served by one transmon | | Swap time per access | ~0.5 μs | other six cells untouched | | Average error per access | ~1.2% per mode | another account says <1.5% | | Cumulative error after 10 accesses | ~11% | assuming independent errors | | Dominant error source | residual inter-mode interactions in the cavity | stated by the team |
Breaking down the addressing process, there are four steps:
1. Select a target cell (say, cell seven). 2. Apply the corresponding frequency control tone. 3. Open the swap; the state moves into the buffer. 4. The transmon operates on the buffer, then the state is written back to cell seven — the other six cells remain untouched, in about 0.5 microseconds.
Why a multimode cavity as the storage layer
The multimode cavity works as storage because of its lifetime. Such seamless cavities have previously achieved photon lifetimes of tens to hundreds of milliseconds, far longer than the coherence times of planar transmons — a two-order-of-magnitude gap. Parking information in the cavity and retrieving it only when needed is physically worthwhile.
For error-corrected machines, the significance lies in the composition of a logical qubit. A surface-code logical qubit spreads across dozens of physical qubits; if part of that function can be replaced by cavity modes, the wiring per logical qubit shrinks.
How long this line has been running
Random-access quantum memory was formalized by Giovannetti, Lloyd, and Maccone in 2008, as a structure queryable in superposition — the core operation of several quantum algorithms with proven exponential speedups.
Hardware lagged. In 2019, a team built a 105-mode random-access memory with atomic ensembles, proving the principle; but the superconducting platform — the leading candidate for fault-tolerant quantum computing — lacked an equivalent. On the computer-architecture side, work by Baker, Schuster, and Chong on quantum architectures with memory argued that random access would reshape how error-corrected machines are organized; hardware just hadn't caught up.
Seamless cavities, with photon lifetimes of tens to hundreds of milliseconds, were natural storage candidates. Schuster's group's 2017 paper, *Random access quantum information processors*, drove a nine-qubit quantum memory with a single transmon; the difference this time is the added buffer layer.
Wiring savings: still a design argument
One caveat deserves its own section: this prototype provides no measured wiring savings. The paper and coverage describe the direction as "fewer signal connections," but the buffer cavity and tunable coupler are hardware too; no count is given of how many control lines the transmon, buffer, and coupler jointly require, nor per-mode storage-time readouts.
Seven modes share one transmon — a 7:1 ratio. Whether it scales with cavity capacity depends on something unverified: the modes sharing one cavity is both why one transmon can address them and the source of crosstalk.
Bottom line: this work's deliverable is a working prototype plus an honest error budget; the wiring savings remain a check yet to be cashed.
Things to watch
- Control-line count: total lines needed by transmon + buffer + coupler versus the seven cells served. Until published, wiring savings stays at the design level.
- Access error after crosstalk suppression: the team lists inter-mode interactions as the next design target; improvements should be judged against 1.2%.
- Cavities with more than seven modes: tests whether crosstalk grows with cell count — key to this architecture serving as a real memory layer.
- Storage-time readouts: comparison against planar transmon coherence times determines whether it can serve as a long-term storage layer.
- Integration with logical-qubit architectures: memory-equipped architectures like those of Baker, Schuster, and Chong need devices like this to enter engineering discussions.
References
1. Li, Gupta et al., random-access quantum memory paper, *Nature Physics* (2026) 2. Phys.org, *Random access quantum memory lets one processor select among seven storage cells*, Ingrid Fadelli, 2026-09-25 3. Scienmag, *Cascaded Quantum Memory Brings Random Access to Superconducting Computers*, 2026-09 4. Naik, Leung, Chakram et al., *Random access quantum information processors* (2017) 5. Giovannetti, Lloyd, Maccone, *Quantum random access memory* (2008)