A surface code protecting one logical qubit at distance 22 costs over a thousand physical qubits. On October 2, fourteen researchers from Google Quantum AI and Google DeepMind posted a 112-page paper on arXiv (arXiv:2610.03682) proposing to cut that number to 36. The trick sounds like sleight of hand: slice the chip into modules, and let the curvature live in the wiring.
Lead authors are Oscar Higgott and HasanGINel Sayginel; co-authors include Craig Gidney, Matt McEwen, Pushmeet Kohli, and Hartmut Neven. Zhiyang He is jointly affiliated with the MIT math department. The paper spans 112 pages with 73 figures and 20 tables; the main text plus methods run 19 pages, with the remaining 93 pages of supplementary material.
Key points
- Modularity is inevitable anyway. A million-qubit monolithic chip hits walls in yield, fabrication, and coupler density. Matt McEwen (Google hardware) proposed the connectivity model: modules stay planar, with long-range couplers only where modules meet. Hyperbolic tilings can be cut into locally flat pieces — all the awkward geometry is pushed into the seams.
- Two code families, two decoders. Modular hyperbolic surface codes and modular hyperbolic color codes, both derived from new semi-hyperbolic code families, were simulated at circuit level in Stim under the SI1000 noise model (0.1% body error rate; cross-module gates set separately at 1%). Surface codes use PyMatching's correlation minimum-weight perfect-matching decoder; color codes use a variant of AlphaQubit, DeepMind's recurrent-attention neural decoder released December 2025.
- Headline numbers. The hyperbolic color code (projected) needs 36 physical qubits per logical qubit at distance 20–24 using 72-qubit modules — over 30x below a comparable surface code and below IBM's bivariate bicycle [[288,12,18]] code at 48, mostly with near-neighbor connectivity. Prior attempts in this direction stalled at roughly 5x savings. The surface-code route shows ~10x overhead reduction reaching 10⁻¹⁰ logical error rate at 120 modules × 116 qubits (13,920 qubits), extrapolating to 15x at larger scales.
- Seam noise barely registers. Sweeping cross-module error rates from 0.1% to 2% with body error fixed at 0.1% barely moves logical error rates, because cross-boundary couplers are a small fraction of total gates. Multi-rate syndrome extraction circuits measure high-weight cross-module stabilizers every three rounds, relaxing speed requirements for slow inter-chip couplers. The 1% cross-module error assumption is grounded in three wiring-resonator experiments (Zhong et al. 2021, Niu et al. 2023, Qiu et al. 2025) already approaching 1% error.
- Computing on cheap memory. Two tools enable logic: code automorphisms (symmetries of the hyperbolic tiling performing logical operations by permuting whole modules) and ribbon extractors (ancilla systems performing surgical measurements of logical Paulis). One extractor serves 100 of the 104 logical qubits in a [[6400, 104, 30]] code at ~22% extra qubits, with the extractor ~4.5x smaller than the code. A 50-bit ripple-carry adder compiled across [[3600, 104, 22]] and [[6400, 104, 30]] memories reports 21,402 qec cycles for ribbon measurements and 28,930 for automorphisms — 428 and 579 cycles per add. At Willow's 1.1 µs surface-code cycle, adding two 50-bit numbers takes roughly 55 ms: dense storage trades time for space.
- All technical figures are from arXiv:2610.03682 (submitted October 2) and public commentary; not all 73 supplementary figures were verified.
- 36, 48, 13,920, 21,402, 28,930, 104, 100, and 22% are paper-disclosed values.
- The 55 ms figure is derived from Willow's 1.1 µs surface-code cycle, not a paper conclusion.
- All results are circuit-level simulations; no hardware experiments are included. The abstract's "over 30x" is a projected, not measured, value.
Caveats: no machine has been built
Every result comes from simulation. The hardware this design assumes is half-real: Willow runs planar surface-code grids below threshold (the paper's physical error model), and wiring resonators near 1% error have been demonstrated — but no one has combined high-performance local grids with high-fidelity cross-module couplers in one system that also tolerates bad qubits and couplers. Defect-handling transfer is stated as an expectation, not a result.
Decoding is the sharper obstacle. Modular hyperbolic codes spread full distance across many modules, defeating the windowing tricks that let real-time decoders work on local surface-code slices. The paper concedes scalable real-time decoding will require parallelized algorithms or dedicated hardware; AlphaQubit decoded the syndrome data in software, but keeping up with a machine emitting syndromes every microsecond is an unsolved engineering problem.
Why it matters
Overhead is the multiplier on every quantum computing forecast. The paper places practical fault tolerance in the ~100k–1M physical qubit range and cites Gidney's own estimate that factoring a 2048-bit RSA integer needs under a million noisy qubits. Cutting per-logical-qubit overhead by ~30x moves all such timelines. The significance is not a delivered machine but turning an unavoidable engineering constraint — chips must be diced — into a free resource: curvature that used to cost extra now hides in wiring you were going to pull anyway.