🔬 Ten Quantum Computers, One Mid-Circuit Test: A Tenfold Gap
Quantum error correction has an unavoidable prerequisite: qubits must be measured mid-computation to detect errors, with the results used to decide subsequent operations and even drive control. This mechanism is called mid-circuit measurement with feed-forward.
The problem: measurement itself perturbs neighboring qubits and forces other qubits to idle while waiting.
Vendors have made competing claims for years. This study measured three vendors' machines with the same yardstick.
The paper is *Evaluating the performance of QEC primitives on quantum processors at large width and depth* by J. A. Montañez-Barrera and Kristel Michielsen of the Jülich Supercomputing Centre (arXiv:2610.05928; publicly reported October 9). It tested 10 processors from Quantinuum, IBM, and IQM. Michielsen also holds a position at the University of Cologne.
📏 Measuring the Components, Not the Whole Machine
The study does not test whether error correction succeeds. It measures the four primitives error correction depends on: mid-circuit measurement, qubit reset, feed-forward control (choosing the next operation based on measurement results), and idle qubits waiting in queue.
This distinction is the paper's most valuable contribution. Headlines about quantum computers are full of qubit counts, but whether error correction can actually run depends on these four small things. (The four-primitive framing comes from consistent reports; the abstract does not itemize them.)
The paper also designed a pre-screening test: estimating whether a chip qualifies without running full experiments. It uses a modified QAOA (Quantum Approximate Optimization Algorithm) whose problem requires the same connectivity and measurements as the target error-correcting code. With each added layer, the degradation of solution quality is observed. On the scoring scale, 1 equals the optimal solution and 0.5 equals random. Circuits ran up to 2,950 mid-circuit measurements.
💥 The Cost of Mid-Circuit Measurement Differs by an Order of Magnitude
The core numbers:
On IBM processors, circuits with mid-circuit measurements had effective error rates roughly ten times those of measurement-free versions. On Quantinuum machines, the added measurement error was roughly equivalent to one ordinary two-qubit gate.
Tenfold versus one two-qubit gate. This is not a question of "which is better"—it is an architectural difference of orders of magnitude.
| Vendor and Model | Effective Error Rate Range | |---|---| | Quantinuum H2-1 | ~0.22% to 0.49% | | Quantinuum Helios-1 | ~0.22% to 0.49% | | IBM Heron and Eagle | ~1.1% to 3.2% |
The paper's interpretation also touches on a known cost of ion traps: on Helios-1, the measurement overhead rises as qubit chains grow longer. The authors attribute this to the number of operations that can run simultaneously: Helios has eight operation zones, of which only four perform two-qubit gates.
🏆 Helios-1's Scores and Its Ceiling
On a surface-code layout with 25 data qubits, Helios-1 scored highest at all tested depths, with per-point gaps of 2 to 4 standard deviations, 50 runs per point.
Scaling up: on an 81-data-qubit surface code, a 91-data-qubit triangular color code, and 48-data-qubit bivariate-bicycle codes (a code family studied for reducing the qubit count needed for error correction), Helios-1 stayed above random.
Note the limit: completing all measurements on a 91-data-qubit layout without failure is not the same as actually correcting errors at that scale. What separates them is decoder real-time performance, crosstalk suppression, and calibration drift handling. The paper measures the former.
The 91-qubit group was especially tight: only 7 of 98 physical qubits could be spared as ancillas, so measurements had to be done in batches—45 mid-circuit measurements per layer.
This must be stated precisely: these numbers prove the processor can sustain intensive error-correction operation patterns; they do not prove errors were actually corrected at that scale. The paper says so itself.
In one other comparison, Helios-1's estimated error rate on a 30-qubit chain was lower, but with uncertainty too wide to confirm improvement from that item alone.
IQM's Emerald and Garnet chips saw signals drop quickly beyond two data qubits of chain length, attributed by the authors to conditional control and wiring limitations.
🔍 One Corroborating Data Point, and How Weak It Is
The paper used protected-memory experiments across 11 zones of IBM's Phoenix processor to validate the pre-screening method itself. Top-scoring zones did show fewer logical errors, with an average deviation of 1.6 ranks, versus 2.1–2.7 for several reference calibration metrics.
The caveat must be clear: this was done only on small surface-code patches, and on only one processor.
The study also found something interesting: when researchers rewrote the schedule to run more gates and measurements in parallel, benchmark scores improved clearly. The improvement came from scheduling, not from changing the chip.
⚖️ What This Study Does Not Claim
- It is a preprint; peer review is incomplete.
- Reports disagree on how many runs the benchmark requires; defer to the paper itself.
- Effective error rates are ranges, not single points; four models share one range, obscuring per-model differences.
- "Measurement cost rises with chain length" was observed on one machine only (Helios-1) and cannot be generalized to all ion-trap architectures.
- The authors say the pre-screening method needs more testing before it can replace full experiments.
- Original tables for the scoring scale (0.5–1) and QAOA problem construction details were not obtained.
- Paper: J. A. Montañez-Barrera and Kristel Michielsen, *Evaluating the performance of QEC primitives on quantum processors at large width and depth*, arXiv:2610.05928; publicly reported 2026-10-09. Preprint, not peer-reviewed.
- All figures (10 processors, tenfold vs. one two-qubit gate, 0.22%–0.49% vs. 1.1%–3.2%, 2–4 standard deviations with 50 runs per point, 81/91/48 data qubits, 7 ancillas of 98 physical qubits, 45 mid-circuit measurements per layer, 2,950 mid-circuit measurements, 0.5–1 scale, IQM signal loss beyond two data qubits, 1.6 vs. 2.1–2.7, four of eight zones for two-qubit gates) are taken from an IRC Junkie report of 2026-10-09. Original arXiv tables were not verified.
- The "four primitives" framing comes from consistent secondary reporting; the abstract does not itemize them.