The most critical distance in a quantum computer lies between the quantum chip and the classical decoder.
Each round of the surface code requires syndrome measurements: instead of looking at qubit states directly, you ask a few questions about the whole system to determine whether and where errors occurred. These questions must reach a classical computer before the quantum state degrades, the decoder must compute corrections, and the instructions must return before the next gate cycle. The entire loop runs on microsecond timescales. If the decoder lags even one step, error correction becomes a memorial service.
On October 13, Alice & Bob (Paris and Boston) announced that its LDPC-cat error correction architecture has, for the first time, been decoded on NVIDIA GPUs, using NVIDIA's low-latency, high-throughput NVQLink channel. This is a dress rehearsal for moving error correction from dedicated hardware onto graphics cards. The official wording is careful: a proof of concept, using synthetic data, not constituting real-time decoding.
The Cat Qubit's Core Strength
Cat qubits, the technology路线 developed by Alice & Bob's founders, are natively resistant to bit flips: continuous nonlinear dissipation exponentially suppresses the dominant physical error. The other half is a 2D low-density parity-check (LDPC) code, with the full design published in Nature Communications in January 2025 (s41467-025-56298-8).
Cats hold down bit flips at the physical layer; LDPC codes gather remaining errors at the logical layer with low overhead. The architecture's target numbers are striking: 100 logical qubits on a chip of 758 cat qubits, with a logical error rate below 10^-8 per cycle. By comparison, early surface code proposals required physical qubit budgets in the hundreds of thousands for a similar logical count.
The cost lands on the decoding side. Cat qubits produce syndromes that are fast and dense; if the classical decoder's throughput can't keep up, the physical-layer advantage is erased. That is exactly the question this rehearsal set out to answer.
What the Pipeline Looks Like
The disclosed integration parameters form a pipeline:
- Quantum processor (cat qubit chip) produces fast, dense syndrome measurements.
- Quantum Machines OPX1000 control hardware exports measurement data.
- Open Acceleration Stack couples the controller directly to GPUs with microsecond-scale round-trip latency.
- NVIDIA NVQLink, an open architecture for fast quantum-classical communication (targeting error decoding, calibration, and hybrid computation), connects to
- NVIDIA GPU clusters, which decode multiple syndrome streams in parallel and return corrections before the next gate cycle.
- Alice & Bob Newsroom, *Alice & Bob decodes LDPC-cat codes on GPUs with NVIDIA NVQLink*, 2026-10-13. https://alice-bob.com/newsroom/alice-bob-decodes/
- Quantum Computing Report, *Alice & Bob Demonstrates GPU Decoding for LDPC-Cat Codes via NVIDIA NVQLink*, 2026-10-14. https://quantumcomputingreport.com/alice-bob-demonstrates-gpu-decoding-for-ldpc-cat-codes-via-nvidia-nvqlink/
- Rémi A. et al., *LDPC-cat codes for low-overhead quantum computing in 2D*, Nature Communications, 2025-01. https://www.nature.com/articles/s41467-025-56298-8
- NVIDIA, *NVQLink Quantum Computing Solutions*. https://www.nvidia.com/en-us/solutions/quantum-computing/nvqlink/
- Quantum Machines, *OPX1000 Control Hardware and Open Acceleration Stack*. https://www.quantum-machines.co/products/opx1000/
Although only a proof of concept, the results show how decoding scales through parallelism: several syndrome streams decoded simultaneously, with efficiency growing with machine size. Alice & Bob's next step is optimizing this pipeline to the performance needed for real-time decoding.
This is not the first collaboration. In March 2026, the companies decoded simulated Elevator code syndrome data on NVIDIA's CUDA-Q platform, running for one hour and fifty-seven minutes. In June 2025, CUDA-Q was integrated into Alice & Bob's quantum simulation library Dynamiqs. The gap between one hour fifty-seven and microsecond round trips is precisely the hurdle this rehearsal aims to clear.
Proven Three Things, and Only Three Things
Proven:
1. LDPC-cat codes can be decoded on NVIDIA GPUs with existing tools—decoding capacity can follow the GPU industry rather than a dead-end dedicated-hardware path. Alice & Bob US General Manager Juliette Peyronnet noted decoding capacity can grow with the machine, with the next step being speed sufficient to keep up with the quantum computer. 2. A microsecond round-trip link exists: OPX1000 + Open Acceleration Stack + NVQLink compresses communication between control electronics and GPU supercomputing to the microsecond scale. 3. Parallel decoding efficiency scales with the number of syndrome streams—the foundation for moving from dedicated decoder chips to GPU clusters.
Not proven (equally important):
1. Synthetic data is not real measurement. The run used pre-generated syndromes, not live chip output—noise structure, timing jitter, and real instrument quirks were absent. 2. Parallel decoding throughput is not the same as errors being corrected. A fast decoder and a reduced logical error rate are two different things. The 758-physical-to-100-logical figures come from the architecture paper's design targets, not measurements from this demonstration. 3. Real-time decoding did not occur. The company itself drew the line: proof of concept; real-time comes next.
A corporate-claim footnote: Alice & Bob states its cat architecture can reduce the hardware needed for a useful large-scale quantum computer by up to 200x versus competing routes—a company statement without third-party verification. The company, founded in 2020, has raised €180 million, employs 250+ people, and counts a Nobel laureate among its advisors.
The Clock Keeps Ticking
In the error correction race: quantum gates tick in nanoseconds, syndrome round trips in microseconds, while decoder compute budgets are measured in milliseconds. Channels like NVQLink push that last figure toward microseconds. GPU cluster parallelism, LDPC code sparsity, and cat qubit physical advantages are aligned on the same pipeline for the first time.
The real-time decoding pipeline is the next gate. Only when live syndrome streams flow into GPU clusters and corrections return to the chip within microseconds will this dress rehearsal become a performance. Until then, 758 and 100 remain ledger targets, and microseconds are merely a score on an empty channel.
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