Core Fusion Explained: Can Two Small Cores Become One Super Single-Thread Core?

Forum topic · ✨步子哥 · 2026-04-28

Summary

This zhichai.net forum post explores a three-decade-old question in processor design: can multiple physical cores be virtually fused into a single logical core to boost single-thread performance? Starting from Intel's 2025 patent EP4579444A1 (Software Defined Super Cores), the author traces the research lineage from Wisconsin's 1996 Multiscalar architecture, through Thread-Level Speculation (TLS/SpMT), Intel's Anaphase prototype, the 2012 CoreFusion study (four small cores matching an 8-wide big core with 35% less area and 28% lower peak power), and the 2019 HPCA hybrid TLS/CoreFusion scheme showing 8-12% gains on SPECint workloads. The post explains why Hyper-Threading is the opposite approach (improving throughput, not single-thread speed), details three core engineering hurdles—instruction stream partitioning, area/power break-even, and compiler/runtime complexity—and discusses the dark silicon dilemma motivating fused small-core designs. If Intel's SDC lands in a future all-E-core chip like rumored Titan Lake (2028), cores could dynamically merge for single-thread bursts.

Overview

A forum post on zhichai.net examines whether two physical CPU cores can be virtually merged into one logical core to dramatically improve single-thread performance. The discussion is anchored by Intel's 2025 patent EP4579444A1 ("Software Defined Super Cores", SDC) and three decades of academic research beginning with the 1996 Multiscalar architecture. The conclusion: theoretically feasible, extremely difficult in practice, but the industry has never given up.

Key points

Hyper-Threading is the opposite direction. SMT (Hyper-Threading) fills idle execution units with a second thread to raise throughput ("1 becomes 2"). It offers almost no benefit for pure single-threaded workloads, which motivates the reverse question: can "2 become 1"?
Multiscalar (1996). Gurindar Sohi's team at Wisconsin proposed slicing a serial program into task blocks executed in parallel across processing units, with hardware managing data dependencies — the founding work of the field.
Thread-Level Speculation (TLS/SpMT, 2000s). CMU (Joel Emer) and UCSD (Dean Tullsen) explored speculatively executing future code blocks on other cores, rolling back on mispredictions. Works well on loop-heavy code; pointer chasing and complex control flow cause high miss rates.
Intel Anaphase (circa 2010). Intel Labs Barcelona built a hardware/software prototype that auto-partitions single-threaded programs across cores, with an ICMC module for inter-core memory coherence. Effective on regular scientific code, weak on branch-heavy general software.
CoreFusion (2012). Four fused small cores matched the single-thread IPC of an 8-wide superscalar big core with 35% less silicon area and 28% lower peak power.
Hybrid TLS/CoreFusion (HPCA 2019). Kim & Yeung's scheme switches between speculation and fusion depending on dependency conflicts, beating either pure approach by 8-12% on hard SPECint2017 workloads (gcc, mcf, omnetpp). Reported IPC gains of 15-40% came at 7-15% extra hardware cost — a thin margin.

Three engineering hurdles

1. Instruction stream partitioning. Data dependencies (e.g., a = b + c; d = a * 2;) must be tracked in real time; any error or added latency destroys the benefit. 2. Area/power break-even. Communication modules, coherence protocols, and checkpoint/rollback logic can erase the small-core area advantage. 3. Compiler and runtime burden. Deciding which blocks can run in parallel and when to fuse demands precise static analysis or dynamic prediction.

Intel's SDC patent (EP4579444A1, 2025)

Intel's "Software Defined Super Cores" patent uses software to split programs into code blocks distributed across small cores, with a shadow store buffer managing data flow and preserving ordering. It points toward a future all-E-core chip (rumored Titan Lake, 2028, with up to 100 E-cores) where cores could temporarily fuse for single-thread bursts and split apart for efficiency. Inter-core communication latency remains the biggest obstacle unless interconnects approach in-core register speeds.

The dark silicon angle

At 2nm-class nodes, power density limits mean much of a chip cannot be powered simultaneously. A fused 4-small-core design may approach the performance of a large 8-wide core (potentially 100W+) at far lower power (~60W), which is why vendors like MediaTek (Dimensity 9400) favor big.LITTLE-style mixes rather than ever-larger monolithic cores.

Conclusion

Core fusion is not a question of *whether it can be done* but *whether it is worth it*. For specific workloads, fusing small cores can match or beat big cores; a universal, transparent, net-positive solution remains unsolved. If Intel ships SDC in a future all-E-core design, it would mark a major pivot in processor design.

References

1. Sohi, G.S., et al. "Multiscalar Processors," ISCA 1996. 2. "A Survey on Thread-Level Speculation Techniques," ACM Computing Surveys, 2016. 3. "Boosting Single-thread Performance in Multi-Core Systems" (Intel Anaphase), ISCA 2009. 4. "Comparing Area and Power of Single-ISA Heterogeneous Multi-core Architectures," IEEE Computer Architecture Letters, 2012. 5. Kim & Yeung, "Exploiting ILP and MLP with Core-Fusion and Thread-Level Speculation," HPCA 2019.