ADS-IMC: Sorting Data Directly Inside 6T SRAM with In-Memory Computation

Forum topic · 小凯 · 2026-05-18

Summary

A forum post on zhichai.net discusses ADS-IMC, an in-memory computing architecture by Dhakad and Vishvakarma (arXiv:2605.16213) that performs sorting entirely within standard 6T SRAM arrays. Sorting is a foundational operation for databases, search engines, and GPUs, but in the von Neumann architecture the cost is dominated by moving data between memory and processor rather than by the sorting algorithm itself. ADS-IMC eliminates this data movement: data is stored in standard weighted binary radix format, and compare-and-swap operations exploit the read/write capabilities of SRAM bit cells on-chip, with no external processor involvement. Unlike prior memristor-based in-memory sorters (e.g., MAGIC-style approaches), ADS-IMC uses the most mature SRAM technology found on every chip. The post reports a 3.4x latency reduction compared to memristor-based designs. Caveats raised include the short 5-page paper that does not specify the exact sorting network (bitonic or odd-even), data width/depth constraints, or the overhead of the peripheral control circuits required for in-SRAM compare-and-swap. References include Kvatinsky et al.'s MAGIC memristor-aided logic and Aga et al.'s Compute Caches (HPCA 2017).

Sorting is one of the most fundamental operations in computing. Databases sort, search engines sort, GPUs sort vertices — but the real cost of sorting goes far beyond algorithmic complexity: data must be moved from memory to the processor, sorted, and written back. The two memory transfers often take longer than the sort itself.

This is the fate of the von Neumann architecture: compute and storage are separate, and data must shuttle back and forth across a narrow channel.

Dhakad and Vishvakarma asked a direct question: what if you sorted inside memory?

The ADS-IMC Architecture

Their architecture, called ADS-IMC, performs sorting entirely within standard 6T SRAM cells. Data is stored in the standard weighted binary radix format — the most natural representation of numbers in computing. Compare-and-swap operations are executed directly on-chip by leveraging the read/write capability of SRAM bit cells, without sending any data to an external processor.

How It Compares to Prior Work

This is not the first in-memory sorting scheme. Previous work used memristor-based in-memory computing sorters, but relied on emerging memory devices. ADS-IMC instead targets the most mature technology — 6T SRAM, the standard cell found in tens of megabytes on every chip. Compared to the memristor-based approach, latency is reduced by 3.4x.

Open Questions

The paper is short (5 pages, 8 figures).
The specific sorting algorithm — bitonic network or odd-even sort — is not clearly stated.
Constraints on data width and sorting depth are not elaborated.
Compare-and-swap inside SRAM requires additional peripheral control circuits; their overhead is not quantified.

References

1. Dhakad, N. S., & Vishvakarma, S. K. (2026). *ADS-IMC: Accelerating Data Sorting with In-Memory Computation*. arXiv:2605.16213 [cs.AR]. 2. Kvatinsky, S., et al. (2014). *MAGIC—Memristor-Aided Logic*. IEEE Transactions on Circuits and Systems II. 3. Aga, S., et al. (2017). *Compute Caches*. IEEE International Symposium on High Performance Computer Architecture (HPCA).