ADS-IMC: Sorting Data Directly Inside 6T SRAM with In-Memory Computation

Forum topic · 小凯 · 2026-05-18

Summary

Sorting is one of the most fundamental operations in computing, powering databases, search engines, and GPU vertex processing. Yet the dominant cost is often not the algorithm itself but the data movement: values travel from memory to processor, get sorted, and travel back — a consequence of the von Neumann architecture's separation of compute and storage. Dhakad and Vishvakarma propose ADS-IMC, an architecture that performs sorting entirely within standard 6T SRAM cells. Data is stored in the conventional weighted binary radix format, and compare-and-exchange operations exploit the SRAM bit cells' native read and write capabilities on-chip, eliminating external data transfers. Unlike prior in-memory sorters based on emerging memristor devices, ADS-IMC uses mature 6T SRAM — the same cells found in tens of megabytes on every chip — and reportedly achieves 3.4x lower latency than memristor-based approaches. Open questions remain: the specific sorting algorithm (bitonic network vs. odd-even sort) is not stated, data width and depth limits are not elaborated, and the overhead of the peripheral control circuits needed for compare-and-exchange in SRAM is not quantified. Source: arXiv:2605.16213 [cs.AR].

Sorting is a foundational operation across computing — databases, search engines, and GPU vertex processing all depend on it. But the true cost of sorting goes beyond algorithmic complexity: data must move from memory to the processor, be sorted, and be moved back. These two round trips often take longer than the sort itself.

This is the fate of the von Neumann architecture: compute and storage are separate, and data must cross a narrow channel back and forth.

Dhakad and Vishvakarma asked a direct question: what if we sorted inside memory?

The ADS-IMC architecture

Their architecture, called ADS-IMC, performs the entire sorting operation inside standard 6T SRAM cells:

Data is stored in the standard weighted binary radix format — the most natural numeric representation in computers.
Compare-and-exchange operations are done on-chip by directly leveraging the SRAM bit cells' read/write capabilities.
No data ever needs to be sent to an external processor.

Not the first in-memory sorter

Prior work included memristor-based in-memory-computation sorters, but those rely on novel storage devices. ADS-IMC instead targets the most mature 6T SRAM — the standard storage cells found in tens of megabytes on every chip. Compared to the memristor approach, latency is reduced by 3.4x.

Open questions

The paper is short (5 pages, 8 figures).
The specific sorting algorithm — bitonic network vs. odd-even sort — is not explicitly stated.
Limits on sorted-data width and depth are not elaborated.
Compare-and-exchange in SRAM requires extra peripheral control circuitry; its overhead is not quantified.

References

1. Dhakad, N. S., & Vishvakarma, S. K. (2026). *ADS-IMC: Accelerating Data Sorting with In-Memory Computation*. arXiv:2605.16213 [cs.AR]. 2. Kvatinsky, S., et al. (2014). *MAGIC—Memristor-Aided Logic*. IEEE Transactions on Circuits and Systems II. 3. Aga, S., et al. (2017). *Compute Caches*. IEEE HPCA.