Systolic arrays are the most common architecture in neural network accelerators. Google's TPU uses them, and so do many AI chips. The reason is simple: they are regular, efficient, and easy to scale. Hundreds or thousands of processing elements (PEs) are arranged in a grid, with data and weights flowing through it like blood, each cell performing one multiply-accumulate operation and passing the result to the next.
But one problem has never been fully solved: when a processing element fails, how do you know which row it is in?
Previous methods could detect that a column contained a fault, but could not localize the specific row within that column. The reason is direct: if you feed the same test data to every row, each row produces the same output pattern. The fault-induced offset is completely mixed with normal offsets and cannot be distinguished.
The FLARE trick: coprime test vectors
FLARE, proposed by Venkatasubramanian, Wan, and Cadambe, uses an elegant mathematical trick: assign each row a coprime integer as its test input. Coprime means these numbers share no common factor — 3 and 5 are coprime, 7 and 11 are coprime, but 3 and 9 are not (common factor 3).
As the test vectors flow through the systolic array, if a PE's weight register is faulty, the output deviation it produces has a special mathematical property: the deviation is exactly divisible by the coprime test input assigned to that row. Because the inputs are pairwise coprime, this divisibility signature uniquely identifies the faulty row — like a set of keys where exactly one opens the lock, so you instantly know which key it was.
Performance
- Under INT16 arithmetic, one test round covers a 256×256 array with localization probability above 0.98
- Test cost is less than 1% of a single inference GEMM block
- If one round is insufficient, a second round using ratio computation precisely locks in the faulty location
- For single-bit errors, odd coprime numbers guarantee one-shot exact localization
- The scheme assumes permanent weight-register faults — transient faults (such as soft errors) behave differently and are not covered by the paper
- How are test vectors actually injected into the array in deployed systems?
- Does the approach still work if the fault occurs in the datapath rather than the weight register?
Open questions
References
1. Venkatasubramanian, L., Wan, Z., & Cadambe, V. (2026). *FLARE: One-Shot PE-Level Fault Localization in Systolic Arrays via Algebraic Test Vectors*. arXiv:2605.08594 [cs.AR]. 2. Jouppi, N. P., et al. (2017). *In-Datacenter Performance Analysis of a Tensor Processing Unit*. ISCA. 3. Kung, H. T. (1982). *Why Systolic Architectures?* IEEE Computer.