Huawei's Tau (τ) Law: When the Endgame of Chips Is Nanoseconds, Not Nanometers
*Translation and summary of a widely shared Chinese tech-forum analysis of Huawei's "Tau Law" announcement at ISCAS 2026.*
Background: The Announcement
On May 25, 2026, at the IEEE International Symposium on Circuits and Systems (ISCAS 2026) in Shanghai, He Tingbo, President of Huawei's Semiconductor Business, presented the "Tau (τ) Law"—a time-scaling principle proposed as the first scaling rule with a shared optimization target across the entire computing stack since Dennard scaling. Six years after her famous "spare tires promoted to mainstream" letter, He argues the industry's core question is no longer "how much smaller can transistors get?" but "what should we optimize toward?" Huawei's answer: time.
Why Moore's Law Is Losing Steam
- Decades of geometric shrinking (90nm → 28nm → 7nm → 3nm → 2nm) are hitting physical and economic walls: quantum tunneling, surging leakage, ~$20B fab costs, and >$1B design costs per leading-edge chip.
- As the forum post puts it: "Moore's Law isn't dead—its cost-effectiveness is."
- Traditional 3D stacking/Chiplets (CoWoS, Foveros, HBM-on-GPU) are back-end processes: separately fabricated dies bonded together—an interface-level "pseudo-3D."
- Logic folding is front-end design: logic within a single module is redistributed across two or more vertically stacked active layers from the start, with signals crossing via TSVs spaced as tight as 1.5 μm—no die-to-die interface penalty.
- Measured results on Kirin 2026 at a fixed process node: 55% higher transistor density and 41% better energy efficiency—equivalent to roughly two process nodes (about three years) of conventional scaling.
- Unified Bus (Lingqu): one unified protocol replacing stacked protocol stacks; cluster communication latency drops from tens of microseconds to ~100 ns (~500x).
- Hi-ONE optical interconnect: 8 Tb/s per module, reach extended from <1 m to 100 m; SerDes distances from ~100 cm to ~5 cm.
- Atlas 960 SuperPod: 15,488 Ascend cards unified as one super node.
- Kirin line: Kirin 9000S (SMIC N+2, ~7nm) in 2023; the upcoming Kirin 2026 uses dual-layer logic folding at 238 MTr/mm² (roughly Intel 18A level, near first-gen TSMC N3), with 3.1 GHz performance cores. Roadmap: 3.39 GHz (2027), 3.71 GHz (2028), 4 GHz+ (2029).
- Ascend line: 910B (7nm N+2), 910C (dual-die, ~800 TFLOPS FP16, ~80% of H100), Ascend 950 in 2026, with logic folding arriving in the 990.
- Physical limits: parasitic R/C, quantum effects, thermal dissipation, and crosstalk at sub-micron TSV pitches.
- Yield and cost: hybrid bonding at 1.5 μm pitch, <0.5 μm overlay precision; the paper itself lists EDA tooling, energy control, and thermal management as unsolved problems.
- Advanced packaging (global market $46B in 2024 → projected $79.4B by 2030, ~23% CAGR for 2.5D/3D): beneficiaries include JCET, TFME, Hua Tian, and SJ Semiconductor.
- EDA: true-3D design flows require new tools; Peking University has already announced a Tau-Law-oriented "true-3D" EDA prototype; Chinese EDA vendors see a historic opening.
- Optical interconnect: demand for silicon photonics and high-speed optical modules grows with AI cluster scale.
The Core Idea: τ = R × C
The time constant τ (resistance × capacitance) measures how fast a circuit responds. Rather than shrinking transistors to indirectly reduce RC delay, Huawei proposes attacking τ directly: signals don't have to travel through smaller transistors—they can travel shorter distances.
Logic Folding: Not 3D Stacking, but "True 3D"
The Four-Layer Optimization Framework
1. Device: HKMG, GAA, strain engineering; the paper notes parasitic R and C now dominate intrinsic delay, so interconnect optimization is more urgent. 2. Circuit: Logic folding shortens critical-path wiring by 50%–80%. 3. Chip: Full software-hardware co-design around τ (pipelining, memory hierarchy, NoC). 4. System:
The paper projects τ in AI systems can shrink to just 10% of the prior year's value annually.
Six Years of Evidence: 381 Chips
Between May 2020 and May 2026, Huawei claims 381 chips designed and mass-produced under these principles, serving over 1 billion users across smartphones (Kirin), AI (Ascend), servers (Kunpeng), automotive, IoT, and industrial control.
The Ambitious 2031 Target
Huawei projects high-end chips will reach 1.4nm-equivalent transistor density by 2031—via logic folding and system optimization on 7nm-class physical processes, not an actual 1.4nm node. Path: from today's 155 MTr/mm² to 400+ MTr/mm² (Kirin 2026 already at 238). Key open questions:
Necessity or Choice?
The forum post argues the Tau Law emerged from constraint: denied EUV lithography since 2019, Huawei couldn't keep competing on node shrinking. But it notes the whole industry—TSMC (SoIC, backside power, High-NA EUV), Intel (Foveros, EMIB)—is also searching for post-Moore paths. Huawei simply went "earlier and more decisively" all-in. As He said: "Huawei hit this wall before its peers."
Industry Implications
Closing Assessment
Whether the Tau Law becomes a true "law" depends on decades of validation, as Moore's Law had. But the forum's conclusion: in the twilight of Moore's Law, Huawei distilled six years of engineering under sanctions into a systematic theory—published openly at a top international conference—arguably the first systematic industrial development framework proposed by a Chinese company in global semiconductors.
References
1. He, T. (2026). *A Time Scaling Theory for Multi-Layer Electronic Systems*. ChinaXiv:202605.00224v1. https://chinaxiv.org/abs/202605.00224 2. He Tingbo keynote, "Exploration and Practice of New Paths in Semiconductors," IEEE ISCAS 2026, Shanghai, May 25, 2026. 3. People's Daily interview with He Tingbo: https://m.thepaper.cn/newsDetail_forward_33252350 4. Yole Group, *Advanced Packaging Market Report 2024–2030*. 5. Peking University School of Integrated Circuits announcement on "true-3D" EDA for logic folding: https://h5.ifeng.com/c/vivo/v002yFF9vvs5R5rZYKYnoyYUofXDcqerKnjCC2cBTOnnIPQ__