Huawei's Tao Law (τ-Scaling): From Nanometers to Nanoseconds in Chip Design

Forum topic · 小凯 · 2026-06-01

Summary

At ISCAS 2026 in Shanghai, Huawei's He Tingbo unveiled the Tao Law (韬定律, tau-scaling), proposing that the semiconductor industry should shift its optimization target from geometric scaling (smaller transistors) to time scaling (shorter signal delays), formalized as τ = R × C. The framework spans four layers: devices, circuits, chips, and systems, anchored by Logic Folding, a front-end design technique that vertically partitions standard cells across stacked active tiers connected by 1.5 µm TSVs, yielding 55% transistor-density and 41% energy-efficiency gains versus planar baselines at the same node. Huawei claims 381 mass-produced chips since 2020 under this principle, with Kirin 2026 reaching 238 MTr/mm² on SMIC N+2 (≈7 nm), approaching TSMC 3 nm density. System-level enablers include the Lingqu unified bus (≈100 ns cluster latency) and Hi-ONE optical interconnect (8 Tb/s, 100 m). Beneficiaries include advanced packaging (JCET, Tongfu, Hua Tian), domestic EDA (Empyrean, Primarius), and silicon photonics vendors. The article assesses technical risks—quantum tunneling, hybrid-bonding yield, EDA maturity—and geopolitical context.

Tao Law (τ-Scaling): Time, Not Transistors, as the New Scaling Target

At IEEE ISCAS 2026 in Shanghai (May 25, 2026), Huawei Director and Semiconductor Business President He Tingbo introduced the Tao Law (韬定律), a multi-layer time-scaling theory for electronic systems. Its central claim: "τ-scaling is, since Dennard scaling, the first scaling principle that establishes a shared optimization target across the entire compute stack." Rather than competing on transistor size, the industry should compete on signal-propagation time, τ = R × C, where R is resistance and C is capacitance.

Key points

1. End of Moore's cost curve

Dennard-style voltage scaling collapsed around the 3–5 nm node; quantum tunneling drives leakage and yield loss.
A leading-edge 3 nm fab now costs ≈US$20 billion; per-transistor cost is rising instead of falling.
He Tingbo: "The industry's central question is no longer 'how much smaller can transistors get?' but 'to what extent should they shrink, and toward what goal?'"

2. The four-layer optimization framework

Devices: high-κ metal gates, GAA, strain engineering; parasitic R and C now exceed intrinsic gate delay, so interconnect dominates.
Circuits: Logic Folding partitions standard cells of a single module across two or more vertically stacked active tiers, joined by ≈1.5 µm pitch TSVs. Critical-path wire length drops 50–80%.
Chips: full-stack instruction- and data-flow co-design; pipeline depth, memory hierarchy, and NoC redesigned around τ.
Systems: Lingqu (灵衢) Unified Bus collapses stacked PCIe/NVLink/InfiniBand/Ethernet stacks to ≈100 ns cluster latency (≈500× lower than legacy). Hi-ONE optical interconnect delivers 8 Tb/s per module over 100 m. The Atlas 960 SuperPod connects 15,488 Ascend cards as a single logical machine. Stated ambition: τ shrinks to ≈10% of the prior year in AI workloads.

3. Logic Folding vs. conventional 3D stacking

Chiplet / CoWoS / Foveros / HBM-on-GPU are *back-end* pseudo-3D integration of pre-fabricated dies via TSVs or micro-bumps.
Logic Folding is a *front-end* design transformation: intra-module cells split across active tiers with sub-1.5 µm hybrid-bonded TSVs and no chip-to-chip interface overhead.
Kirin 2026 measured results at a fixed node: +55% transistor density, +41% energy efficiency, equivalent to roughly two node generations (≈3 years) of conventional Moore scaling.

4. Six years of silicon, not slideware

2020–2026: 381 mass-produced chips under the Tao Law principles, spanning smartphones (Kirin), AI accelerators (Ascend), servers (Kunpeng), automotive, IoT, and industrial. Cumulative users exceed 1 billion.
Kirin 9000S (Mate 60 Pro, 2023) on SMIC N+2 (≈7 nm).
Kirin 2026 (autumn 2026): dual-tier Logic Folding, 238 MTr/mm², approaching TSMC 3 nm density on a ≈7 nm physical node; performance cores at 3.1 GHz.
Roadmap through Kirin 2029 (>4 GHz).
Ascend 910B (SMIC 7 nm N+2), 910C (FP16 ≈800 TFLOPS, ≈80% of NVIDIA H100), 950 (2026), 990 with Logic Folding; ≈100× AI hardware integration growth projected by 2035.

5. The 1.4 nm-equivalent claim for 2031

Target: 400+ MTr/mm² on existing ≈7 nm-class processes via multi-tier folding + device/system optimization.
TSMC reference: N2 in H2 2025, A14 (~1.4 nm) around 2028.
Open questions: physical limits as TSV pitch approaches 1 µm (quantum effects, thermal, crosstalk); hybrid-bonding yield at 1.5 µm pitch with <0.5 µm overlay and <1.5 µm TSV CD; cost vs. TSMC's leading-edge nodes. The Huawei paper itself flags EDA toolchains, energy management, and thermal design as unresolved.

6. Geopolitical context

Hua Tao Law is a response to the 2019 sanctions that cut Huawei off from TSMC and EUV. SMIC's N+2 (DUV multi-patterning) tops out near 7 nm.
The framework is a forced detour, but the underlying limits affect the entire industry; TSMC (SoIC, backside power, High-NA EUV) and Intel (Foveros, EMIB) are pursuing parallel paths. Huawei's pressure accelerated its all-in commitment.

7. Industry beneficiaries

Advanced packaging: Yole projects the market from US$46 B (2024) to US$79.4 B (2030); 2.5D/3D CAGR ≈23%. JCET (Huawei core OSAT), Tongfu Microelectronics (>60% of Ascend 910 2.5D packaging), Hua Tian, and Shenge IC (unlisted, ≈85% of 2.5D advanced packaging) are positioned.
Domestic EDA: Logic Folding demands a true-3D design flow (intra-module partitioning, cross-die interconnect, vertical thermal co-optimization). Peking University's IC School has prototyped "true-3D" EDA tooling for the Tao Law. Empyrean (华大九天) and Primarius (概伦电子) face a strategic window.
Silicon photonics: Hi-ONE needs high-density photonic devices; optical module and photonic-chip demand will rise with cluster scale.

8. An invitation to the industry

He Tingbo: "Toolchains, standards, benchmarks, device physics, and economic models all need contributions beyond any single company."
Required ecosystem: foundries (SMIC, YMTC, CXMT) advancing processes; EDA vendors rebuilding flows; OSATs mastering hybrid bonding yield; silicon-photonics vendors scaling production; academia validating models; standards bodies adopting the new optimization target.

9. Outlook

Whether Tao Law becomes a true "law" depends on decades of validation, just as Moore's Law did.
Autumn 2026 Kirin 2026 silicon will be the first major empirical checkpoint.
The paper is described as the first time a Chinese company has publicly proposed a systematic industry-development principle for global semiconductors.

References

1. He, T. (2026). *A Time Scaling Theory for Multi-Layer Electronic Systems*. ChinaXiv:202605.00224v1. https://chinaxiv.org/abs/202605.00224 2. He Tingbo. (2026). *Keynote: Exploring and Practicing New Semiconductor Pathways*. IEEE ISCAS 2026, Shanghai, May 25, 2026. 3. People's Daily interview with He Tingbo (2026). https://m.thepaper.cn/newsDetail_forward_33252350 4. Yole Group. (2025). *Advanced Packaging Market Report 2024-2030*. 5. Peking University School of Integrated Circuits. (2026). Progress on "true-3D" EDA for Tao Law Logic Folding. https://h5.ifeng.com/c/vivo/v002yFF9vvs5R5rZYKYnoyYUofXDcqerKnjCC2cBTOnnIPQ__