On August 18, a team from the National University of Defense Technology published paper arXiv 2608.03948 introducing THQLink—a quantum-classical heterogeneous decoding architecture based on the domestic TH-Express high-speed interconnect network. Measured average round-trip latency across the entire interconnect link is 2.944 microseconds, 23.3% lower than NVIDIA NVQLink's 3.839 microseconds. Moreover, while NVQLink has only completed network loopback testing and has not yet demonstrated full closed-loop real-time decoding, THQLink has completed an end-to-end 1-microsecond real-time decoding demonstration on a distance-19 surface code.
THQLink's core proposition is specific: use general-purpose HPC clusters as the decoding engine, tightly coupled to quantum control systems via a high-speed interconnect, avoiding the dilemma between "algorithm-frozen dedicated FPGA/ASIC decoders" and "high network latency on general-purpose CPU/GPU systems." The architecture has three layers: on the quantum control side, FPGAs implement the TH-Express physical and link layer protocols with integrated syndrome-to-packet conversion logic; TH-Express switches build a non-blocking, full-line-rate switching fabric; and on the HPC side, general-purpose compute nodes run decoding algorithms plus preprocessing tasks like communication, task scheduling, and correction mapping.
Scalability is the architecture's biggest engineering highlight: each additional compute node adds only 130 nanoseconds of incremental latency. This means when future quantum hardware requires decoding clusters spanning hundreds or thousands of logical qubits, the added communication overhead remains controllable. Traditional PCIe direct-attach schemes are limited by chassis space, and NVIDIA NVQLink is weighed down by the full Ethernet protocol stack, whereas THQLink—via a parallel-window decoding strategy and domestic high-speed networking—moves "real-time decoding" from "runs on one machine" to "scales across clusters."
Why the Parallel-Window Decoding Strategy Scales Code Distance
Traditional global decoding processes syndrome data across all space-time dimensions at once, with computation growing exponentially with error-correction rounds. THQLink's parallel-window strategy splits the full syndrome stream into Type-A and Type-B windows: A windows run in parallel and resolve core regions, with unresolvable boundary defects converted into "artificial boundary defects" passed to B windows; B windows process boundary defects at the seams in parallel. As long as cluster compute is sufficient, total decoding time does not grow with the number of correction rounds. Under test conditions of 0.1% physical error rate and 10x code-distance correction rounds, the parallel-window scheme achieves 1-microsecond real-time decoding of a distance-19 surface code—global decoding manages only distance 11 under the same conditions, an 8x+ expansion in code distance capability.
Head-to-Head Against NVIDIA NVQLink
NVQLink is NVIDIA's RoCE-Ethernet-based solution for quantum-supercomputing coupling, with a published average round-trip latency of 3.839 microseconds—but it retains the overhead of the complete Ethernet protocol stack and has only completed loopback testing. THQLink posts better numbers on three dimensions: 2.944-microsecond round-trip latency, end-to-end closed-loop real-time decoding (distance-19 surface code), and cross-chassis horizontal scaling (+130 ns per hop). The architecture is also not tied to any specific decoding algorithm—MWPM, union-find, and machine-learning decoders can all be deployed directly—and adapts to superconducting, neutral-atom, and trapped-ion quantum hardware platforms.
Current Limitations and Next Steps
The present work remains a prototype validation. Experiments used an AMD Virtex UltraScale+ FPGA to simulate the quantum control system; a real QPU has not yet been directly attached. Multi-rack and very-large-cluster capability rests mainly on architectural design and single-hop incremental latency results, and requires further validation under large-scale concurrent traffic. Load variation across logical qubits, switch fabric congestion, tail latency, and heterogeneous node scheduling will be the next engineering challenges. The team plans to migrate and validate the architecture on quantum low-density parity-check (qLDPC) codes and to develop adaptive load-balancing mechanisms for heterogeneous compute clusters.
What It Changes
THQLink moves real-time quantum error correction decoding from the narrow path of "dedicated hardware that is hard to scale" onto the wide road of "general-purpose HPC clusters + domestic high-speed networking + parallel software stacks." This represents more than the engineering increment of a single paper: it is China's first hardware-level solution for the quantum-supercomputing coupling stack that goes head-to-head with NVIDIA. As qubit counts advance from "tens" toward "thousands," real-time decoding scalability will become the bottleneck before qubits themselves do—if THQLink's route proves out, the "middle layer" of fault-tolerant quantum computing will no longer belong to NVIDIA alone.