On August 18, a team from the National University of Defense Technology released paper 2608.03948 on arXiv, proposing THQLink — a quantum-classical heterogeneous decoding architecture built on China's domestic TH-Express high-speed interconnect network. The measured average round-trip latency of the full interconnect link is 2.944 microseconds, 23.3% lower than NVIDIA NVQLink's 3.839 microseconds. Moreover, while NVQLink has only completed network loopback testing without a full closed-loop real-time decoding demonstration, THQLink has already completed an end-to-end 1-microsecond real-time decoding demonstration of a distance-19 surface code.
THQLink's core proposition is specific: use general-purpose HPC clusters as the decoding engine, tightly coupled to quantum control systems via a high-speed interconnect, avoiding the dilemma between "algorithm-frozen dedicated FPGA/ASIC decoders" and "high network latency with general-purpose CPU/GPU solutions." Three layers make up the system: on the quantum control side, FPGAs implement the TH-Express physical and link layer protocols with integrated syndrome-to-packet conversion logic; TH-Express switches build a non-blocking, full-line-rate switching fabric; and on the HPC side, general-purpose compute nodes run decoding algorithms along with pre/post-processing such as communication, task scheduling, and correction mapping.
Scalability is the architecture's biggest engineering highlight: each additional compute node adds only 130 nanoseconds of incremental latency. This means that when future quantum hardware requires decoding clusters of hundreds or thousands of logical qubits, the extra communication overhead remains controlled. Traditional PCIe direct-attach solutions are constrained by chassis space, and NVIDIA's NVQLink is weighed down by the full Ethernet protocol stack overhead. THQLink, using a parallel-window decoding strategy and domestic high-speed networking, moves real-time decoding from "runs on a single machine" to "scales across clusters."
Why the Parallel-Window Decoding Strategy Handles Larger Code Distances
Traditional global decoding processes all syndrome data across all spatiotemporal dimensions at once, with computational cost growing exponentially with correction rounds. THQLink's parallel-window strategy splits the full syndrome stream into Category A and Category B windows — A windows run in parallel to resolve core regions, with undecidable boundary defects converted into "artificial boundary defects" passed to B windows; B windows process the boundary defects at the seams in parallel. As long as cluster compute is sufficient, total decoding time does not grow with the number of correction rounds. Under test conditions of 0.1% physical error rate and 10x code-distance correction rounds, the parallel-window approach achieves 1-microsecond real-time decoding of a distance-19 surface code, while global decoding under the same conditions only reaches distance 11 — an 8x+ extension in decodable code distance.
Head-to-Head Advantages Over NVIDIA NVQLink
NVQLink is NVIDIA's RoCE-Ethernet-based solution for quantum-supercomputing coupling, with a publicly reported average round-trip latency of 3.839 microseconds, but it retains overhead from the complete Ethernet protocol stack and has only completed loopback testing. THQLink posts better results across three dimensions: 2.944-microsecond round-trip latency, end-to-end closed-loop real-time decoding (distance-19 surface code), and cross-chassis horizontal scaling (+130 ns per hop). The architecture is also not tied to any specific decoding algorithm — MWPM, union-find, and machine-learning decoders can all be deployed directly, and it adapts to superconducting, neutral-atom, and ion-trap quantum hardware platforms.
Current Limitations and Next Steps
The current work remains prototype-stage validation. The experiments used AMD Virtex UltraScale+ FPGAs to simulate the quantum control system, without direct connection to a real QPU; multi-rack and large-scale cluster capability is supported mainly by the architectural design and single-hop incremental latency results, and still needs verification under large-scale concurrent traffic. Load fluctuation across logical qubits, switch network congestion, tail latency, and heterogeneous node scheduling will be the engineering challenges going forward. The team plans to migrate and validate the architecture for quantum low-density parity-check (qLDPC) codes and to develop adaptive load-balancing mechanisms for heterogeneous compute clusters.
What It Changes
THQLink moves real-time quantum error correction decoding from the narrow path of "dedicated hardware that is hard to scale" to the broad path of "general-purpose HPC clusters + domestic high-speed networking + a parallel software stack." This represents more than a single paper's engineering increment: it is the first time China has delivered a hardware-level solution comparable to NVIDIA's in the quantum-supercomputing coupling stack. As qubit counts advance from "dozens" toward "thousands," real-time decoding scalability will become the bottleneck before qubit counts themselves do. With THQLink's route proven viable, NVIDIA is no longer the only option for the "middle layer" of fault-tolerant quantum computing.