HRL Laboratory's July *Nature* cover paper (reviewed in Xinhua's international quantum science column on August 19, 2026) marks a shift for silicon-based quantum computing from a "physics bottleneck phase" to an "engineering integration phase": a 4K cryo-CMOS controller, an mK-temperature exchange-only qubit chip, and superconducting interconnects are now combined inside one commercial dilution refrigerator.
What the 4K CMOS controller does
Traditional architectures require coaxial cables from room temperature (300 K) down to the mK stage for every qubit, causing heat leakage, cabling congestion, and crosstalk as qubit counts grow. HRL's approach:
- 4K cryogenic CMOS controller sits at the 4 K stage instead of room temperature;
- One 1 cm-wide flex cable with ~300 superconducting striplines connects the controller to the quantum chip at mK;
- Controller power ≤ 3.5 W, while electron temperature is maintained around 150 mK;
- Crosstalk better than -80 dB;
- 250 MHz clock rate, generating baseband voltage pulses for qubit control directly in silicon;
- Room-temperature electronics now only send digital instructions and power — waveforms are generated by the CMOS itself.
- [5,1,5] repetition code (distance 5): logical error rate of 5×10⁻³, lower than distance-3's 2.4×10⁻³ — errors are exponentially suppressed as expected with increasing code distance;
- [[4,2,2]] quantum error detection code: after processing all error-detection measurements, 95% fidelity for two logical qubit states; only 59% if error-detection measurements are ignored.
- With LRU: detector event rates stay stable;
- Without LRU: leakage accumulates and error rates grow round over round.
- The "HRL" on this Nature cover is no longer an independent entity;
- Industry successors to the silicon route are IBM + Intel + Diraq;
- This paper is effectively HRL's final, complete answer sheet showing silicon quantum computing has moved from the physics-bottleneck phase to the engineering-integration phase.
- Whether IBM integrates HRL's 4K CMOS controller design into a future generation of Heron / Nighthawk / Kookaburra;
- Whether Intel, already making high-density silicon quantum dot chips on standard CMOS lines, reuses HRL's 4K CMOS design;
- Whether Diraq can reproduce the [5,1,5] repetition code and [[4,2,2]] error detection code on its own platform using this public answer sheet.
This means the "brain" of future large-scale quantum computers can be fully embedded at the 4 K stage — a key step toward manageable operating costs.
18 exchange-only qubits: from 2 to 18 in three years
Exchange-only qubits encode 0/1 in the eigenstate subspace of three electron spins. They require no magnetic field and no microwaves — only baseband pulses tuning exchange interactions, which is favorable for scaling. The engineering challenge: each qubit needs three quantum dots and precise tuning.
| Metric | Value | Notes | |---|---|---| | Qubit count | 18 (exchange-only) | 3×6 square lattice, 54 quantum dots | | Single-qubit gate fidelity | 99.98% | average, cumulative distribution | | Two-qubit CNOT fidelity | 99.65% | average | | T₂\* | 19.3 μs | decoherence time | | N_osc / Q factor | 674 | oscillations within coherence time | | CNOT estimated error rate | 0.02% | derived from T₂\* | | 3-year progress | 2 qubits → 18 qubits | engineering acceleration | | CMOS controller | ≤ 3.5 W | operating at 4 K | | Superconducting striplines | 296 lines, 1 cm wide | crosstalk < -80 dB | | Wafer process | 200 mm wafer scale | CMOS-compatible backend integration |
The US Department of Energy has announced a 99.9999%-pure ²⁸Si program — meaning the physical devices and the control hardware for silicon qubits are, for the first time, available within the same temperature architecture.
Both encoding defenses demonstrated: [5,1,5] and [[4,2,2]]
Exchange-only qubits are prone to leakage into four S=3/2 subspaces outside the computational basis. HRL inserted an LRU (Leakage Reduction Unit) in each error-correction round:
Leakage management has thus moved from a research topic to a mandatory engineering step per correction round.
What HRL's dissolution means — an end and a new beginning
"HRL's team has disbanded due to funding; its core was acquired by IBM, with some staff absorbed by Intel, Diraq, and other silicon quantum computing companies."
In other words:
What to watch over the next 12 months:
The real question: how far behind superconducting / neutral atoms?
At 18 qubits, silicon holds the current record for this platform, but superconducting systems are already running error correction on 100+ qubits (Zuchongzhi 3.2 / Willow / Condor), and neutral-atom platforms entangle 300+ atoms. Silicon's next stop in the integration phase is "50+ qubits + code distance beyond 7 + inter-chip interconnect" — estimated at 18–24 months away.
Silicon is back
At the industry level, this paper delivers in one package: the engineering interface (4K CMOS), the physical device (exchange-only qubits), and the encoding scheme ([5,1,5] + [[4,2,2]] + LRU). It's a victory for 18 qubits — and more importantly, proof that silicon can finally deploy the chip industry's core strength: engineering integration.
Watch one thing over the next 12–18 months: whether IBM's next-generation Kookaburra / Cockatoo quantum chips adopt HRL's 4K CMOS control paradigm. If that happens, the significance of this work will need to be re-priced.