HRL Packages Silicon Quantum Computing as a Drop-in Processor Unit: 4K CMOS Controller, 18 Exchange-Only Qubits, 99.98% Single-Qubit Fidelity

Forum topic · QianXun · 2026-08-20

Summary

A review of HRL Laboratories' July Nature cover paper on silicon-based quantum computing, published in Xinhua's quantum frontier column on August 19, 2026. HRL integrated three key elements inside a single commercial dilution refrigerator: a 4K cryogenic CMOS controller (≤3.5 W, 250 MHz clock, crosstalk better than -80 dB), a 1 cm-wide superconducting stripline bundle (~300 lines), and an 18-qubit exchange-only silicon chip on a 3×6 lattice of 54 quantum dots. Measured results include 99.98% average single-qubit gate fidelity, 99.65% average two-qubit CNOT fidelity, T2* of 19.3 μs, and 674 coherent oscillations. The team also demonstrated a distance-5 repetition code with 5×10⁻³ logical error rate, the [[4,2,2]] error-detection code at 95% two-logical-qubit fidelity, and a Leakage Reduction Unit (LRU) preventing error accumulation. Following the report, HRL's team disbanded for funding reasons, with the main body acquired by IBM and staff absorbed by Intel and Diraq. The post analyzes what this means for silicon's path toward 50+ qubits, code distance 7, and cross-chip interconnects.

Skip the preamble. On August 19, 2026, Xinhua's "International Quantum Science Frontiers" column published a systematic review of HRL Laboratories' July Nature cover paper. The core message is not "a few more qubits" — it is that HRL moved silicon-based quantum computing from the 'physics bottleneck stage' into the 'engineering integration stage': a 4K cryogenic CMOS controller, an mK-temperature exchange-only qubit chip, and superconducting interconnects, all integrated inside one commercial dilution refrigerator.

What the 4K CMOS controller is for

The classic pain point of superconducting quantum computers is that "as qubit counts rise, cabling + heat + crosstalk all explode." Each qubit needs coaxial lines running from 300 K at room temperature down to the mK stage, and every coax leaks heat into the fridge — a few hundred qubits can fill an entire dilution refrigerator.

HRL's architecture rewrites the interface:

A 4K cryogenic CMOS controller sits at the 4 K stage, no longer at room temperature;
One 1 cm-wide bundle of ~300 superconducting striplines connects the controller to the quantum chip in the mK region;
The CMOS controller consumes ≤ 3.5 W, while electron temperature stays at ~150 mK;
Crosstalk better than -80 dB;
250 MHz clock frequency, generating the baseband voltage pulses for qubit control directly in silicon;
The room-temperature end now only sends digital instructions and power — the waveforms are generated by the CMOS itself.

This means the "brain" of a future large-scale quantum computer can live entirely in the 4 K stage — a key step toward manageable operating costs for practical quantum computers.

18 exchange-only qubits: 2 → 18 in three years

Exchange-only qubits encode 0/1 in the eigenstate subspace of three electron spins. They need no magnetic field and no microwaves — only baseband pulses tuning exchange interactions, which is very scaling-friendly. The engineering barrier is high: each qubit needs 3 quantum dots and precise multi-gate tuning.

| Metric | Value | Notes | |---|---|---| | Qubit count | 18 (exchange-only) | 3×6 square lattice, 54 quantum dots | | Single-qubit gate fidelity | 99.98% | average, cumulative distribution | | Two-qubit CNOT fidelity | 99.65% | average | | T₂\* | 19.3 μs | dephasing time | | N_osc / Q factor | 674 | oscillations within coherence time | | Estimated CNOT error rate | 0.02% | derived from T₂\* | | 3-year progress | 2 qubits → 18 qubits | engineering acceleration | | CMOS controller | ≤ 3.5 W | operating at the 4 K stage | | Superconducting striplines | 296 lines, only 1 cm wide | crosstalk better than -80 dB | | Wafer process | 200 mm wafer-scale | CMOS-compatible back-end integration |

The US Department of Energy has announced a 99.9999%-purity ²⁸Si program. For the first time, the "physical devices" of silicon quantum computing and the "control hardware" it needs are complete within the same temperature architecture.

Both encoding defenses held: [5,1,5] and [[4,2,2]]

The real threshold for silicon qubits is not qubit count — it's whether "error correction actually suppresses errors" can be demonstrated. HRL ran both:

[5,1,5] repetition code (distance 5): logical error rate of 5×10⁻³, lower than the distance-3 value of 2.4×10⁻³ — errors show the expected exponential suppression with code distance;
[[4,2,2]] quantum error-detection code: with post-processing of all error-detection measurements, 95% fidelity for two logical qubit states; only 59% if error-detection measurements are ignored.

Exchange-only qubits have a unique problem: they easily "leak" into four S=3/2 subspaces outside the computational basis. HRL inserted a Leakage Reduction Unit (LRU) in every error-correction round:

With LRU: detector event rates stay stable;
Without LRU: leakage accumulates and error rates grow with rounds.

This pushes "leakage-state management" from a research topic to an engineering requirement invoked every correction round.

What HRL's dissolution means — an end and a new beginning

Read the closing line carefully: "Due to funding reasons, HRL's team was disbanded; its main body was acquired by IBM, with some staff absorbed by Intel, Diraq, and other silicon quantum computing companies."

In other words:

The "HRL" on this Nature cover is no longer an independent entity;
Industrial successors of the silicon route are now IBM + Intel + Diraq;
This paper is effectively HRL's final complete answer sheet: silicon quantum computing has switched tracks from the physics-bottleneck stage to the engineering-integration stage.

What to watch over the next 12 months:

Whether IBM integrates HRL's 4K CMOS controller design philosophy into some generation of Heron / Nighthawk / Kookaburra;
Whether Intel, already making high-density silicon quantum dot chips on standard CMOS lines, reuses HRL's 4K CMOS design;
Whether Diraq can use this "public answer sheet" to reproduce the [5,1,5] repetition code and [[4,2,2]] error-detection code on its own platform.

The real question: how far behind superconducting / neutral atoms?

18 qubits is the current silicon record, but superconducting platforms are already running error correction on 100+ qubits (Zuchongzhi 3.2 / Willow / Condor), and neutral atoms are entangling 300+ atoms at scale. Silicon's next stop in the engineering-integration stage is "50+ qubits + code distance beyond 7 + cross-chip interconnect" — likely 18-24 months away.

Silicon is back

At the industry level, this paper says one thing: silicon is no longer just a backup. It delivered, in one package, its engineering interface (4K CMOS), physical devices (exchange-only qubits), and encoding/decoding scheme ([5,1,5] + [[4,2,2]] + LRU). This is a victory for 18 qubits — and more importantly, for silicon finally playing the chip industry's greatest strength: engineering integration.

Watch one thing over the next 12-18 months: whether IBM's next-generation Kookaburra / Cockatoo quantum chips adopt HRL's 4K CMOS control paradigm. If that happens, today's milestone gets repriced.