HBM Roadmap Divergence (Mid-Term Trend): Samsung 'Stacks' vs. SK Hynix 'Connects' — The Big Three's Roadmaps at Hot Chips 2026

Research date: 2026-08-25 | Time horizon: 2026–2030 | Sources: Hot Chips 2026, ISSCC 2026, GTC 2026, Counterpoint, TrendForce

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One-Line Conclusion

HBM is no longer a standard part sitting next to the GPU — it is becoming a semi-custom compute component co-designed with the GPU. Three to five years from now, market share will not be decided by stack height, but by who can design HBM as part of the accelerator itself.

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Introduction: One Conference, Three Destinies

At the Hot Chips 2026 tutorial day (early morning of August 24, 2026, Beijing time), all three memory giants centered their talks on HBM:

• Micron fired first: compute grows ~3x every two years while HBM bandwidth grows less than 2x — "the memory wall has not disappeared; it may actually get worse." Citing Meta Llama3 405B data: HBM3 faults accounted for 17.2% of unplanned interruptions.
• Samsung responded: moving the base die from DRAM process to a 4nm logic process, turning HBM from passive storage into an "active computing partner." The endgame zHBM stacks DRAM vertically on top of the GPU — vs. HBM4E: 70% lower IO power, +230% DRAM bandwidth, 100W saved per GPU.
• SK Hynix closed: MR-MUF process holds up 16-Hi HBM4, hybrid bonding is reserved for HBM5 (skipping HBM4E), and Intel's EMIB is folded into the 2.5D roadmap.

Three days, three talks, three routes, three destinies.

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Three Routes in One Sentence Each

| Vendor | Route | One-liner | Key bet | |---|---|---|---| | Samsung | Stacks | Design HBM as part of the accelerator | 4nm logic base die + zHBM 3D ultimate stacking | | SK Hynix | Connects | Take vertical interconnect to the extreme | MR-MUF + EMIB + hybrid bonding at HBM5 | | Micron | Reality | Survive on efficiency and reliability | 1bn-class process (one generation behind) + Llama3 reliability lens |

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Key Technical Differences

Samsung: cHBM → aHBM → zHBM, a Three-Phase Path

• Phase 1 cHBM4 (landing 2026): 4nm logic base die + D2D interface + memory controllers moved onto the die; recovers 5-10% of XPU area, +10-20% performance, HPB cooling cuts peak temperature by 35%+
• Phase 2 aHBM (2027-2028): base die integrates RAS, ATE, near-memory compute PEs — addressing KV-cache bloat from context windows growing ~30x per year
• Phase 3 zHBM (trial production 2028-2030): removes the 2.5D interposer entirely; DRAM stacked vertically on top of the GPU; depends on WoW + HCB processes

SK Hynix: MR-MUF as the Workhorse, Hybrid Bonding Held for HBM5

• Today: MR-MUF (mass reflow molded underfill) supports 16-Hi HBM4 — 48GB per stack, >2 TB/s bandwidth
• Physical ceiling: JEDEC's HBM4 height cap of 775μm (conveniently aligned to 300mm logic wafer thickness); at 20-Hi the bonding method must change
• Future: VP Lee Jae-sik stated clearly that "hybrid bonding won't be ready before HBM4E; HBM5 is the earliest viable generation" — at 20-Hi, bump pitch <18μm, thermal resistance down 35%, core dies can thicken 24%
• Packaging alliance: SK Hynix's 2.5D roadmap also adopts Intel's EMIB, benchmarked alongside CoWoS-S/R/L
• HBF (High Bandwidth Flash): jointly announced with SanDisk — 512GB capacity, 0.4-3.0 TB/s bandwidth, positioned between HBM and SSD; alliance includes Google and Tenstorrent

Micron: Memory-Wall Realism

• Cites Meta Llama3 405B training data: during a 54-day pretraining run, HBM3 faults caused 17.2% of unplanned interruptions; ~78% of unplanned interruptions were hardware-related
• Next-gen HBM must compete not just on speed, but on error correction, test, telemetry, and fault isolation
• 2026 capacity fully sold out; FY2027 capex will rise sharply, focused on HBM and DRAM

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The Compute-vs-Bandwidth Scissors Gap

| Dimension | Growth since 2017 | Implication | |---|---|---| | Compute | ~3x every two years (A100→B100→B200→R200) | The scissors gap keeps widening | | HBM bandwidth | Less than 2x every two years | Even if HBM bandwidth doubled yearly, it couldn't keep up |

This is the real driver of roadmap divergence — relying on more layers and more pins for bandwidth is hitting diminishing returns.

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Mid-Term Timeline

| Time | Milestone | |---|---| | 2026 Q1 | Samsung first to mass-produce HBM4 (11.7 Gbps / 3.3 TB/s / 36GB 12-Hi) | | 2026 Q2 | SK Hynix 12-Hi HBM4 mass production; Samsung HBM4E samples | | 2026 H2 | Samsung HBM4 exceeds 60% of its HBM shipments; NVIDIA Vera Rubin ships | | 2027 H1 | Full mass production of 16-Hi HBM4; all three reach 48GB | | 2028 | Samsung HBM5 prototype mass production, introduces HPB | | 2028-2030 | Hybrid bonding enters HBM5; zHBM trial production; CXMT starts HBM3E | | 2029-2030 | Counterpoint forecasts full mass production of HBM hybrid bonding | | 2030+ | The 20-Hi / 24-Hi era begins |

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Implications for Chinese Players

• 3-4 year gap: CXMT's HBM3 in small-batch trial production by end of 2026, scaling in 2027 (50k wafers/month target); samples already sent to Huawei Ascend
• 2030 target: 12-15% domestic HBM localization rate
• Counterpoint analyst MS Hwang: "Before at least 2030, Chinese players will find it hard to catch up with the Korean giants in high-end DRAM and HBM"
• Side effect: the big three's HBM drain keeps the global DRAM shortage running through 2027 (Nikkei: by late 2027 supply will meet only 60% of demand); Gartner forecasts 2026 global PC shipments -10.4% and smartphones -8.4%

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The Takeaway

> HBM has moved from "standard part" to "semi-custom compute component" — the coming war is a war of "co-design with the accelerator," not a war of "stacking more layers."

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Appendix: The full research includes a six-dimension comparison matrix, Samsung's three-phase roadmap diagram, a mid-term timeline, and a source appendix:

• HTML version: 深度研究_HBM路线分化_2026-08-25.html
• MD version: 深度研究_HBM路线分化_2026-08-25.md

A follow-up comment will add the full six-dimension comparison matrix, the source appendix, and three open discussion questions. Corrections welcome.