HBM Roadmap Divergence (Mid-Term Trend): Samsung Stacks vs SK hynix Connects vs Micron Reality — Hot Chips 2026 Panorama

Research date: 2026-08-25 | Time horizon: 2026-2030 | Sources: Hot Chips 2026, ISSCC 2026, GTC 2026, Counterpoint, TrendForce

One-Line Conclusion

HBM is no longer a standard component sitting next to the GPU — it is becoming a semi-custom compute component co-designed with the GPU. Three to five years from now, market share will not be decided by stack count, but by who can design HBM as part of the accelerator itself.

Introduction: One Conference, Three Destinies

At Hot Chips 2026 tutorial day (early morning Beijing time, 2026-08-24), all three memory giants centered their presentations on HBM:

• Micron fired first: compute roughly triples every two years while HBM bandwidth grows less than 2x — "the memory wall hasn't disappeared; it may get worse." Citing Meta Llama3 405B data: HBM3 faults accounted for 17.2% of unplanned interruptions.
• Samsung countered: moving the Base Die from DRAM process to a 4nm logic process, turning HBM from passive storage into an "active compute partner." The endgame, zHBM, stacks DRAM vertically on top of the GPU — vs HBM4E: 70% lower IO power, 230% more DRAM bandwidth, 100W saved per GPU.
• SK hynix closed: MR-MUF process carries 16-Hi HBM4, hybrid bonding is reserved for HBM5 (skipping HBM4E), and Intel's EMIB is folded into the 2.5D roadmap.

Three days, three presentations, three routes, three destinies.

The Three Routes in One Line Each

| Vendor | Route | One-liner | Key Bet | |---|---|---|---| | Samsung | Stacks | Design HBM as part of the accelerator | 4nm logic Base Die + zHBM ultimate 3D stacking | | SK hynix | Connects | Take 3D interconnection to the extreme | MR-MUF + EMIB + hybrid bonding held for HBM5 | | Micron | Reality | Survive on efficiency and reliability | 1bnm process (one generation behind) + Llama3 reliability lens |

Key Technical Differences

Samsung: cHBM → aHBM → zHBM Three-Phase Path

• Phase 1, cHBM4 (landing 2026): 4nm logic Base Die + D2D interface + memory controllers moved on-die, reclaiming 5-10% of XPU area; +10-20% performance; HPB cooling cuts peak temperature by 35%+
• Phase 2, aHBM (2027-2028): Base Die integrates RAS, ATE, and near-memory compute PEs, addressing KV-cache inflation as context windows grow ~30x per year
• Phase 3, zHBM (trial production 2028-2030): eliminates the 2.5D interposer; DRAM stacked vertically atop the GPU, relying on WoW + HCB processes

SK hynix: MR-MUF as Mainstay, Hybrid Bonding Bet on HBM5

• Today: MR-MUF (mass reflow molded underfill) sustains 16-Hi HBM4 — 48GB per stack, >2 TB/s bandwidth
• Physical ceiling: JEDEC HBM4 height limit of 775μm (aligned with 300mm logic wafer thickness); the 20-Hi era requires a new bonding method
• Future: VP Lee Jae-sik stated clearly that "hybrid bonding won't be ready before HBM4E; HBM5 is the earliest generational landing point" — at 20-Hi, bump pitch <18μm, thermal resistance down 35%, core die can be 24% thicker
• Packaging alliance: SK hynix's 2.5D roadmap also adopts Intel EMIB, compared side-by-side with CoWoS-S/R/L
• HBF (High Bandwidth Flash): jointly announced with SanDisk — 512GB capacity, 0.4-3.0 TB/s bandwidth, positioned between HBM and SSD; alliance includes Google and Tenstorrent

Micron: Memory-Wall Realism

• Cites Meta Llama3 405B training data: over 54 days of pretraining, HBM3 faults caused 17.2% of unplanned interruptions; ~78% of unplanned interruptions were hardware-related
• Next-gen HBM must compete not just on speed but on error correction, test, telemetry, and fault isolation
• 2026 capacity fully sold out; FY2027 capex to increase substantially, focused on HBM and DRAM

The Compute vs. Bandwidth Scissors Gap

| Dimension | Growth since 2017 | Implication | |---|---|---| | Compute | ~3x every two years (A100→B100→B200→R200) | Scissors gap keeps widening | | HBM bandwidth | Under 2x every two years | Even if HBM doubles yearly, it cannot catch up |

This is the real driver of roadmap divergence — stacking more layers and pins for bandwidth is hitting diminishing returns.

Mid-Term Timeline

| Time | Milestone | |---|---| | 2026 Q1 | Samsung first to mass-produce HBM4 (11.7 Gbps / 3.3 TB/s / 36GB 12-Hi) | | 2026 Q2 | SK hynix 12-Hi HBM4 mass production; Samsung HBM4E sampling | | 2026 H2 | Samsung HBM4 exceeds 60% of its HBM shipments; NVIDIA Vera Rubin ships | | 2027 H1 | HBM4 16-Hi at full mass production; all three vendors at 48GB | | 2028 | Samsung HBM5 prototype production, introducing HPB | | 2028-2030 | Hybrid bonding enters HBM5; zHBM trial production; CXMT starts HBM3E | | 2029-2030 | Counterpoint forecasts full HBM hybrid-bonding mass production | | 2030+ | 20-Hi and 24-Hi era begins |

Implications for China

• 3-4 year generation gap: CXMT's HBM3 small-batch trial production by end of 2026, scaling in 2027 (target: 50,000 wafers/month), samples already sent to Huawei Ascend
• 2030 target: 12-15% domestic HBM substitution rate
• Counterpoint analyst MS Hwang: "Before at least 2030, Chinese players will find it hard to catch the Korean giants in high-end DRAM and HBM"
• Side effect: the three giants' crowding-out effect keeps the global DRAM shortage running through 2027 (Nikkei: only 60% of demand met by end-2027); Gartner forecasts 2026 global PC shipments -10.4% and smartphones -8.4%

Closing Quote

> HBM has moved from "standard component" to "semi-custom compute component" — the war ahead is one of co-design with the accelerator, not of stacking more layers.

Appendix: The full research includes a six-dimension comparison matrix, Samsung's three-phase roadmap diagram, a mid-term timeline, and a source appendix (available in the original HTML/MD files referenced on the forum). A follow-up comment will add the full comparison matrix, source appendix, and three open discussion questions.